Chipset Configuration Registers
10.1.70 SBEMC3—Scheduled Break Event C3 Exit Latency
Offset Address: 3300–3303h
Attribute:
Size:
R/W
32-bit
Default Value:
00000000h
Bit
Description
31:23
22:16
15
Reserved.
Present State C3 Future State C3 Exit Latency (C3C3EL) — R/W.
Sets exit latency if present and future C-state is C3.
Reserved.
Present State C2 Future State C3 Exit Latency (C2C3EL) — R/W.
14:8
7
Sets exit latency if present C-state is C2 and future C-state is C3.
Reserved.
Present State C0 Future State C3 Exit Latency (C0C3EL) — R/W.
6:0
Sets exit latency if present C-state is C0 and future C-state is C3.
10.1.71 SBEMC4—Scheduled Break Event C4 Exit Latency
Offset Address: 3304–3307h
Attribute:
Size:
R/W
32-bit
Default Value:
00000000h
Bit
Description
31
Reserved.
Present State C4 Future State C4 Exit Latency (C4C4EL) — R/W.
30:24
Sets exit latency if present and future C-state is C4.
Present State C3 Future State C4 Exit Latency (C3C4EL) — R/W.
22:16
15
Sets exit latency if present C-state is C3 and future C-state is C4.
Reserved.
Present State C2 Future State C4 Exit Latency (C2C4EL) — R/W.
14:8
7
Sets exit latency if present C-state is C2 and future C-state is C4.
Reserved.
Present State C0 Future State C4 Exit Latency (C0C4EL) — R/W.
6:0
Sets exit latency if present C-state is C0 and future C-state is C4.
342
Datasheet
INTEL [ INTEL ]
