Functional Description
5.13.5.5
POPDOWN (Auto C2 to C3/C4)
After returning to the C2 state from C3/C4, it the PDME bit (D31:F0: Offset A9h: bit 4)
is set, the platform can return to a C3 or C4 state (depending on where it was prior to
going back up to C2). This behaves similar to the Deferred C3/C4 transition, and will
keep the processor in a C2 state until:
• Bus masters are no longer active.
• A break event occurs. Note: Bus master traffic is not a break event in this case.
5.13.6
Sleep States
5.13.6.1
Sleep State Overview
The ICH10 directly supports different sleep states (S1–S5), which are entered by
setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states is
based on several assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor can only perform one register access at a time. A request to Sleep
always has higher priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled
throttling. Note that thermal throttling cannot be disabled, but setting the SLP_EN
bit disables thermal throttling (since S1–S5 sleep state has higher priority).
• The G3 state cannot be entered via any software mechanism. The G3 state
indicates a complete loss of power.
5.13.6.2
Initiating Sleep State
Sleep states (S1–S5) are initiated by:
• Masking interrupts, turning off all bus master enable bits, setting the desired type
in the SLP_TYP field, and then setting the SLP_EN bit. The hardware then attempts
to gracefully put the system into the corresponding Sleep state.
• Pressing the PWRBTN# Signal for more than 4 seconds to cause a Power Button
Override event. In this case the transition to the S5 state is less graceful, since
there are no dependencies on observing Stop-Grant cycles from the processor or
on clocks other than the RTC clock.
• Assertion of the THRMTRIP# signal will cause a transition to the S5 state. This can
occur when system is in S0 or S1 state.
Table 5-30. Sleep Types
Sleep Type
Comment
Intel ICH10 asserts the STPCLK# signal. This lowers the processor’s power
consumption. No snooping is possible in this state.
S1
S3
ICH10 asserts SLP_S3#. The SLP_S3# signal controls the power to non-critical
circuits. Power is only retained to devices needed to wake from this sleeping
state, as well as to the memory.
ICH10 asserts SLP_S3# and SLP_S4#. The SLP_S4# signal shuts off the power to
the memory subsystem. Only devices needed to wake from this state should be
powered.
S4
S5
Same power state as S4. ICH10 asserts SLP_S3#, SLP_S4# and SLP_S5#.
Datasheet
151
INTEL [ INTEL ]
