Functional Description
PCI Express ports and the (G)MCH (via DMI) have the ability to cause PME using
messages. When a PME message is received, ICH10 will set the PCI_EXP_STS bit. If the
PCI_EXP_EN bit is also set, the ICH10 can cause an SCI via the GPE1_STS register.
PCI Express has a Hot-Plug mechanism and is capable of generating a SCI via the GPE1
register. It is also capable of generating an SMI. However, it is not capable of
generating a wake event.
5.13.5
Dynamic Processor Clock Control
The ICH10 has extensive control for dynamically starting and stopping system clocks.
The clock control is used for transitions among the various S0/Cx states, and processor
throttling. Each dynamic clock control method is described in this section. The various
sleep states may also perform types of non-dynamic clock control.
The ICH10 supports the ACPI C0, C1, C2, C3, and C4 states.
The Dynamic Processor Clock control is handled using the following signals:
• STPCLK#: Used to halt processor instruction stream.
• STP_CPU#: Used to stop processor’s clock
• DPSLP#: Used to force Deeper Sleep for processor.
• DPRSLPVR: Used to lower voltage of VRM during C4 state.
• DPRSTP#: Used to alert the processor of C4 state. Also works in conjunction with
DPRSLPVR to communicate to the VRM whether a slow or fast voltage ramp should
be used.
The C1 state is entered based on the processor performing an auto halt instruction.
The C2 state is entered based on the processor reading the Level 2 register in the
ICH10.
The C2 state can also be entered from C3 or C4 states if bus masters require snoops
and the PUME bit (D31:F0: Offset A9h: bit 3) is set.
The C3 state is entered based on the processor reading the Level 3 register in the
ICH10 and when the C4onC3_EN bit is clear (D31:F0:Offset A0:bit 7). This state can
also be entered after a temporary return to C2 from a prior C3 or C4 state.
The C4 state is entered based on the processor reading the Level 4 register in the
ICH10, or by reading the Level 3 register when the C4onC3_EN bit is set. This state can
also be entered after a temporary return to C2 from a prior C4 state.
A C1, C2, C3, or C4 state ends due to a Break event. Based on the break event, the
ICH10 returns the system to C0 state.
Table 5-29 lists the possible break events from C2, C3, or C4. The break events from
C1 are indicated in the processor’s datasheet.
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Datasheet
INTEL [ INTEL ]
