Functional Description
Table 5-29. Break Events
Breaks
from
Event
Comment
IRQ[0:15] when using the 8259s, IRQ[0:23]
for I/O APIC. Since SCI is an interrupt, any SCI
will also be a break event.
Any unmasked interrupt goes
active
C2
Any internal event that cause an
NMI or SMI#
C2
C2
Many possible sources
Any internal event that cause
INIT# to go active
Could be indicated by the keyboard controller
via the RCIN input signal.
Need to wake up processor so it can do snoops
Any bus master request
(internal, external or DMA, or
BMBUSY#) goes active and
BM_RLD=1 (D31:F0:Offset
PMBASE+04h: bit 1)
Note: If the PUME bit (D31:F0: Offset A9h: bit
3) is set, then bus master activity will NOT be
treated as a break event. Instead, there will be
a return only to the C2 state.
C3, C4
Only available if FERR# enabled for break event
indication (See FERR# Mux Enable in GCS,
Chipset Config Registers:Offset 3410h:bit 6)
Processor Pending Break Event
Indication
C2
C2
Can be sent at any time after the Ack-C2
message and before the Ack-C0 message,
when not in C0 state.
REQ-C0 Message from (G)MCH
5.13.5.1
Slow C4 Exit
In order to eliminate the audible noise caused by aggressive voltage ramps when
exiting C4 the states at a regular, periodic frequency, the ICH10 supports a method to
slow down the voltage ramp at the processor VR for certain break events. If enabled for
this behavior, the ICH10 treats IRQ0 and IRQ8 as “slow” break events since both of
these can be the system timer tick interrupt. Rather than carefully tracking the
interrupt and timer configuration information to track the one correct interrupt, it was
deemed acceptable to simplify the logic and slow the break exit sequence for both
interrupts. Other break event sources invoke the normal exit timings.
The ICH10 indicates that a slow voltage ramp is desired by deasserting DPRSTP#
(high) and leaving DPRSLPVR asserted (high). The normal voltage ramp rate is
communicated by deasserting DPRSTP# (high) and deasserting DPRSLPVR (low).
The ICH10 waits an additional delay before starting the normal voltage ramp timer
during the C4 or C5 exit sequence. If a “fast” break event occurs during the additional,
slow-Exit time delay, the ICH10 quickly deasserts DPRSLPVR (low), thereby speeding
up the voltage ramp and reducing the delay to a value that is typically seen by the
device in the past. In the event that a fast break event and a slow break event occur
together, the fast flow is taken.
Datasheet
149
INTEL [ INTEL ]
