Functional Description
Table 5-28. Causes of SMI# and SCI (Sheet 2 of 2)
Cause
SCI
No
SMI
Additional Enables
Where Reported
TCO SMI — Write attempted
to BIOS
Yes
BIOSWP=1
BIOSWR_STS
BIOS_RLS written to
GBL_RLS written to
Write to B2h register
Periodic timer expires
64 ms timer expires
Yes
No
No
No
No
No
GBL_EN=1
GBL_STS
Yes
Yes
Yes
Yes
BIOS_EN=1
BIOS_STS
APMC_EN = 1
PERIODIC_EN=1
SWSMI_TMR_EN=1
APM_STS
PERIODIC_STS
SWSMI_TMR_STS
Enhanced USB Legacy
Support Event
No
No
Yes
Yes
LEGACY_USB2_EN = 1 LEGACY_USB2_STS
Enhanced USB Intel Specific
Event
INTEL_USB2_EN = 1
INTEL_USB2_STS
UHCI USB Legacy logic
Serial IRQ SMI reported
No
No
Yes
Yes
LEGACY_USB_EN=1
none
LEGACY_USB_STS
SERIRQ_SMI_STS
Device monitors match
address in its range
No
No
Yes
Yes
none
DEVTRAP_STS
SMB_SMI_EN
Host Controller
Enabled
SMBus Host Controller
SMBus host status reg.
SMBus Slave SMI message
No
No
Yes
Yes
none
none
SMBUS_SMI_STS
SMBUS_SMI_STS
SMBus SMBALERT# signal
active
SMBus Host Notify message
received
HOST_NOTIFY_INTRE
N
SMBUS_SMI_STS
HOST_NOTIFY_STS
No
Yes
Access microcontroller 62h/
66h
No
No
Yes
Yes
MCSMI_EN
MCSMI_STS
SLP_EN bit written to 1
SMI_ON_SLP_EN=1
SMI_ON_SLP_EN_STS
USB2_EN=1,
Write_Enable_SMI_En
able=1
USB Per-Port Registers Write
Enable bit changes to 1.
USB2_STS, Write
Enable Status
No
Yes
Write attempted to BIOS
No
No
Yes
Yes
BIOSWPD = 0
BIOSWR_STS
GPIO Lockdown Enable bit
changes from ‘1’ to ‘0’.
GPIO_UNLOCK_SMI_E GPIO_UNLOCK_SMI_S
N=1 TS
NOTES:
1.
2.
3.
4.
5.
SCI_EN must be 1 to enable SCI. SCI_EN must be 0 to enable SMI.
SCI can be routed to cause interrupt 9:11 or 20:23 (20:23 only available in APIC mode).
GBL_SMI_EN must be 1 to enable SMI.
EOS must be written to 1 to re-enable SMI for the next 1.
ICH10 must have SMI# fully enabled when ICH10 is also enabled to trap cycles. If SMI# is
not enabled in conjunction with the trap enabling, then hardware behavior is undefined.
Only GPI[15:0] may generate an SMI# or SCI.
When a power button override first occurs, the system will transition immediately to S5.
The SCI will only occur after the next wake to S0 if the residual status bit (PRBTNOR_STS)
is not cleared prior to setting SCI_EN.
6.
7.
8.
This SMI is a synchronous event.
Datasheet
147
INTEL [ INTEL ]
