Functional Description
5.13.5.2
Transition Rules among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and
throttling states:
• Entry to any S0/Cx state is mutually exclusive with entry to any S1–S5 state. This
is because the processor can only perform one register access at a time and Sleep
states have higher priority than thermal throttling.
• When the SLP_EN bit is set (system going to a S1 - S5 sleep state), the THTL_EN
and FORCE_THTL bits can be internally treated as being disabled (no throttling
while going to sleep state).
• If the THTL_EN or FORCE_THTL bits are set, and a Level 2, Level 3 or Level 4 read
then occurs, the system should immediately go and stay in a C2, C3 or C4 state
until a break event occurs. A Level 2, Level 3 or Level 4 read has higher priority
than the software initiated throttling.
• After an exit from a C2, C3 or C4 state (due to a Break event), and if the THTL_EN
or FORCE_THTL bits are still set the system will continue to throttle STPCLK#.
Depending on the time of break event, the first transition on STPCLK# active can
be delayed by up to one THRM period (1024 PCI clocks = 30.72 µs).
• The Host controller must post Stop-Grant cycles in such a way that the processor
gets an indication of the end of the special cycle prior to the ICH10 observing the
Stop-Grant cycle. This ensures that the STPCLK# signals stays active for a
sufficient period after the processor observes the response phase.
• If in the C1 state and the STPCLK# signal goes active, the processor will generate a
Stop-Grant cycle, and the system should go to the C2 state. When STPCLK# goes
inactive, it should return to the C1 state.
5.13.5.3
Deferred C3/C4
Due to the new DMI protocol, if there is any bus master activity (other than true
isochronous), then the C0 to C3 transition will pause at the C2 state. ICH10 will keep
the processor in a C2 state until:
• ICH10 sees no bus master activity.
• A break event occurs. In this case, the ICH10 will perform the C2 to C0 sequence.
Note that bus master traffic is not a break event in this case.
To take advantage of the Deferred C3/C4 mode, the BM_STS_ZERO_EN bit must be
set. This will cause the BM_STS bit to read as 0 even if some bus master activity is
present. If this is not done, then the software may avoid even attempting to go to the
C3 or C4 state if it sees the BM_STS bit as 1.
If the PUME bit (D31:F0: Offset A9h: bit 3) is 0, then the ICH10 will treat bus master
activity as a break event. When reaching the C2 state, if there is any bus master
activity, the ICH10 will return the processor to a C0 state.
5.13.5.4
POPUP (Auto C3/C4 to C2)
When the PUME bit (D31:F0: Offset A9h: bit 3) is set, the ICH10 enables a mode of
operation where standard (non-isochronous) bus master activity will not be treated as
a full break event from the C3 or C4 states. Instead, these will be treated merely as
bus master events and return the platform to a C2 state, and thus allow snoops to be
performed.
After returning to the C2 state, the bus master cycles will be sent to the (G)MCH, even
if the ARB_DIS bit is set.
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Datasheet
INTEL [ INTEL ]
