Functional Description
Table 5-26. State Transition Rules for Intel® ICH10
Present
Transition Trigger
State
Next State
• Processor halt instruction
• Level 2 Read
• G0/S0/C1
• G0/S0/C2
• Level 3 Read
• G0/S0/C3 or G0/S0/C4 - depending on
C4onC3_EN bit (D31:F0:Offset A0h:bit
7) and BM_STS_ZERO_EN bit
• Level 4 Read
G0/S0/C0
• SLP_EN bit set
(D31:F0:Offset A9h:bit 2)
• Power Button Override
• G1/Sx or G2/S5 state
• G2/S5
• Mechanical Off/Power Failure
• G3
• Any Enabled Break Event
• G0/S0/C0
• G0/S0/C2
• G2/S5
• G3
• STPCLK# goes active
G0/S0/C1
• Power Button Override
• Power Failure
• Any Enabled Break Event
• G0/S0/C0
• G2/S5
• G3
• Power Button Override
G0/S0/C2
• Power Failure
• Previously in C3/C4 and bus
masters idle
• C3 or C4 - depending on PDME bit
(D31:F0: Offset A9h: bit 4)
• Any Enabled Break Event
• Any Bus Master Event
• G0/S0/C0
• G0/S0/C2 - if PUME bit (D31:F0: Offset
A9h: bit 3) is set, else G0/S0/C0
G0/S0/C3
• Power Button Override
• G2/S5
• G3
• Power Failure
• Previously in C4 and bus
masters idle
• C4 - depending on PDME bit (D31:F0:
Offset A9h: bit 4
• Any Enabled Break Event
• G0/S0/C0
• Any Bus Master Event
G0/S0/C4
• G0/S0/C2 - if PUME bit (D31:F0: Offset
A9h: bit 3) is set, else G0/S0/C0
• Power Button Override
• Power Failure
• G2/S5
• G3
• Any Enabled Wake Event
• Power Button Override
• Power Failure
• G0/S0/C0
• G2/S5
• G3
G1/S1,
G1/S3, or
G1/S4
• Any Enabled Wake Event
• Power Failure
• G0/S0/C0
• G3
G2/S5
G3
• Power Returns
• Optional to go to S0/C0 (reboot) or G2/
S5 (stay off until power button pressed
or other wake event). (See Note 1)
NOTES:
1.
Some wake events can be preserved through power failure.
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Datasheet
INTEL [ INTEL ]
