Functional Description
5.13.3
System Power Planes
The system has several independent power planes, as described in Table 5-27. Note
that when a particular power plane is shut off, it should go to a 0 V level.
s
Table 5-27. System Power Plane
Controlled
Plane
By
Description
The SLP_S3# signal can be used to cut the power to the processor
completely. The DPRSLPVR support allows lowering the processor’s
voltage during the C4 state.
SLP_S3#
signal
CPU
When SLP_S3# goes active, power can be shut off to any circuit
not required to wake the system from the S3 state. Since the S3
state requires that the memory context be preserved, power must
be retained to the main memory.
SLP_S3#
MAIN
signal
The processor, devices on the PCI bus, LPC I/F, and graphics will
typically be shut off when the Main power plane is shut, although
there may be small subsections powered.
When the SLP_S4# goes active, power can be shut off to any
circuit not required to wake the system from the S4. Since the
memory context does not need to be preserved in the S4 state,
the power to the memory can also be shut down.
SLP_S4#
signal
MEMORY
SLP_S5#
signal
When SLP_S5# goes active, power can be shut to any circuit not
required to wake the system from the S5 state. Since the memory
context does not need to be preserved in the S5 state, the power
to the memory can also be shut.
This pin is asserted when the manageability platform goes to MOff.
Depending on the platform, this pin may be used to control the
(G)MCH, ICH controller link power planes, the clock chip power,
and the SPI flash power.
Link
SLP_M#
Controller
Individual subsystems may have their own power plane. For
example, GPIO signals may be used to control the power to disk
drives, audio amplifiers, or the display screen.
DEVICE[n]
GPIO
5.13.4
SMI#/SCI Generation
On any SMI# event taking place, ICH10 asserts SMI# to the processor, which causes it
to enter SMM space. SMI# remains active until the EOS bit is set. When the EOS bit is
set, SMI# goes inactive for a minimum of 4 PCI clocks. If another SMI event occurs,
SMI# is driven active again.
The SCI is a level-mode interrupt that is typically handled by an ACPI-aware operating
system. In non-APIC systems (which is the default), the SCI IRQ is routed to one of the
8259 interrupts (IRQ 9, 10, or 11). The 8259 interrupt controller must be programmed
to level mode for that interrupt.
In systems using the APIC, the SCI can be routed to interrupts 9, 10, 11, 20, 21, 22, or
23. The interrupt polarity changes depending on whether it is on an interrupt shareable
with a PIRQ or not (see Section 13.1.3). The interrupt remains asserted until all SCI
sources are removed.
Table 5-28 shows which events can cause an SMI# and SCI. Note that some events can
be programmed to cause either an SMI# or SCI. The usage of the event for SCI
(instead of SMI#) is typically associated with an ACPI-based system. Each SMI# or SCI
source has a corresponding enable and status bit.
Datasheet
145
INTEL [ INTEL ]
