Functional Description
5.4.1.5
SYNC
Valid values for the SYNC field are shown in Table 5-9.
Table 5-9.
SYNC Bit Definition
Bits[3:0]
Indication
Ready: SYNC achieved with no error. For DMA transfers, this also indicates DMA
request deassertion and no more transfers desired for that channel.
0000
Short Wait: Part indicating wait-states. For bus master cycles, the Intel® ICH10
does not use this encoding. Instead, the ICH10 uses the Long Wait encoding
(see next encoding below).
0101
0110
Long Wait: Part indicating wait-states, and many wait-states will be added. This
encoding driven by the ICH10 for bus master cycles, rather than the Short Wait
(0101).
Ready More (Used only by peripheral for DMA cycle): SYNC achieved with
no error and more DMA transfers desired to continue after this transfer. This
value is valid only on DMA transfers and is not allowed for any other type of
cycle.
1001
1010
Error: Sync achieved with error. This is generally used to replace the SERR# or
IOCHK# signal on the PCI/ISA bus. It indicates that the data is to be transferred,
but there is a serious error in this transfer. For DMA transfers, this not only
indicates an error, but also indicates DMA request deassertion and no more
transfers desired for that channel.
NOTES:
1.
2.
All other combinations are RESERVED.
If the LPC controller receives any SYNC returned from the device other than short (0101),
long wait (0110), or ready (0000) when running a FWH cycle, indeterminate results may
occur. A FWH device is not allowed to assert an Error SYNC.
5.4.1.6
5.4.1.7
SYNC Time-Out
There are several error cases that can occur on the LPC interface. The ICH10 responds
as defined in section 4.2.1.9 of the Low Pin Count Interface Specification, Revision 1.1
to the stimuli described therein. There may be other peripheral failure conditions;
however, these are not handled by the ICH10.
SYNC Error Indication
The ICH10 responds as defined in section 4.2.1.10 of the Low Pin Count Interface
Specification, Revision 1.1.
Upon recognizing the SYNC field indicating an error, the ICH10 treats this as an SERR
by reporting this into the Device 31 Error Reporting Logic.
110
Datasheet
INTEL [ INTEL ]
