Functional Description
Each of the 3 LED's may be configured to use one of a variety of sources for output
indication. The MODE bits control the LED source:
• LINK_100/1000 is asserted when link is established at either 100 or 1000Mbps.
• LINK_10/1000 is asserted when link is established at either 10 or 1000Mbps.
• LINK_UP is asserted when any speed link is established and maintained.
ACTIVITY is asserted when link is established and packets are being transmitted or
received.
• LINK/ACTIVITY is asserted when link is established AND there is NO transmit or
receive activity
• LINK_10 is asserted when a 10Mbps link is established and maintained.
• LINK_100 is asserted when a 100Mbps link is established and maintained.
• LINK_1000 is asserted when a 1000Mbps link is established and maintained.
• FULL_DUPLEX is asserted when the link is configured for full duplex operation.
• COLLISION is asserted when a collision is observed.
• PAUSED is asserted when the device's transmitter is flow controlled.
• LED_ON is always asserted; LED_OFF is always de-asserted.
The IVRT bits allow the LED source to be inverted before being output or observed by
the blink-control logic. LED outputs are assumed to normally be connected to the
negative side (cathode) of an external LED.
The BLINK bits control whether the LED should be blinked while the LED source is
asserted, and the blinking frequency (either 200 ms on and 200 ms off or 83 ms on
and 83 ms off). The blink control may be especially useful for ensuring that certain
events, such as ACTIVITY indication, cause LED transitions, which are sufficiently
visible to a human eye. The same blinking rate is shared by all LEDs.
5.3.6
Function Level Reset Support (FLR)
The Gigabit LAN Controller supports the Function Level Reset (FLR) capability. The FLR
capability can be used in conjunction with Intel Virtualization Technology. FLR allows an
Operating System in a Virtual Machine to have complete control over a device,
including its initialization, without interfering with the rest of the platform. The device
provides a software interface that enables the Operating System to reset the whole
device as if a PCI reset was asserted.
5.3.6.1
FLR Steps
5.3.6.1.1
FLR Initialization
1. A FLR is initiated by software writing a 1 to the Initiate FLR bit.
2. All subsequent requests targeting the Function will not be claimed and will be
Master Abort Immediate on the bus. This includes any configuration, I/O or
Memory cycles, however, the Function shall continue to accept completions
targeting the Function.
5.3.6.1.2
FLR Operation
Function will Reset all configuration, I/O and memory registers of the Function except
those indicated otherwise and reset all internal states of the Function to the default or
initial condition.
106
Datasheet
INTEL [ INTEL ]
