Functional Description
5.4.1.3
Cycle Type / Direction (CYCTYPE + DIR)
The ICH10 always drives bit 0 of this field to 0. Peripherals running bus master cycles
must also drive bit 0 to 0. Table 5-7 shows the valid bit encodings.
Table 5-7.
Cycle Type Bit Definitions
Bits[3:2]
Bit1
Definition
00
00
01
01
10
10
0
1
0
1
0
1
I/O Read
I/O Write
Memory Read
Memory Read
DMA Read
DMA Write
Reserved. If a peripheral performing a bus master cycle generates this
value, the Intel ICH10 aborts the cycle.
11
x
5.4.1.4
Size
Bits[3:2] are reserved. The ICH10 always drives them to 00. Peripherals running bus
master cycles are also supposed to drive 00 for bits 3:2; however, the ICH10 ignores
those bits. Bits[1:0] are encoded as listed in Table 5-8.
Table 5-8.
Transfer Size Bit Definition
Bits[1:0]
Size
00
01
8-bit transfer (1 byte)
16-bit transfer (2 bytes)
Reserved. The Intel ICH10 never drives this combination. If a peripheral running
a bus master cycle drives this combination, the ICH10 may abort the transfer.
10
11
32-bit transfer (4 bytes)
Datasheet
109
INTEL [ INTEL ]
