Host Bridge (D0:F0)
7.2.2
DID—Identification Register
Offset:
Default Value:
02h–03h
810xh
Attribute:
Size:
RO
16 bits
Default
Bit
and
Description
Access
8100-
8107h
RO
Device ID (DID): This is a 16-bit value assigned to the controller. Refer
to the Intel® SCH Specification Update for the DID for various product
SKU.
15:0
7.2.3
PCICMD—PCI Command Register
Offset:
Default Value:
04h–05h
0007h
Attribute:
Size:
R/W, RO
16 bits
Default
and
Bit
Description
Access
0
RO
15:3
Reserved
1
RO
Bus Master Enable (BME): The Intel® SCH is always enabled as a bus
master.
2
1
0
1
RO
Memory Space Enable (MSE): The Intel® SCH is always allowed to
access memory.
1
RO
I/O Access Enable (IOAE): The memory controller always allows access
to I/O.
7.2.4
7.2.5
PCISTS—PCI Status Register
Offset:
Default Value:
06h–07h
0000h
Attribute:
Size:
RO
16 bits
Default
Bit
and
Description
Access
0000h
RO
15:0
Reserved
RID—Revision Identification Register
Offset Address:
Default Value:
08h
TBD
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
TBD
RO
Revision ID: This value is tied to the value in the LPC bridge (Device 31,
Function 0).
7:0
Datasheet
83
INTEL [ INTEL ]
