Host Bridge (D0:F0)
7.1.3
CPU BIST Strap
To enter CPU BIST, software first sets the PMSW.CBE (BIST enable) bit, and then does a
warm reset by writing to RSTC.WARM. The BIST strap sequence is as follows:
• As part of the boot sequence, the power management controller will check whether
PMSW.CBE has been set. If so, it will set the state of the BIST bit in the POC vector
accordingly.
• The power management controller prepares the full POC vector and writes it to the
HPOC register internally. These values are driven onto the HA[31:3] and INIT#
pins.
• CPURST# is deasserted to the processor after ensuring that at least 4 host bus
clocks have elapsed after driving POC.
• POC pins all take their normal usage two host clocks after CPURST# deassertion.
7.2
Host PCI Configuration Registers
Table 19.
Host Bridge Configuration Register Address Map
Offset
Mnemonic
VID
Register Name
Vendor ID
Default
8086
Type
00h–01h
02h–03h
04h–05h
06h–07h
08h
RO
RO
DID
Device ID
8100-8107
0007h
PCICMD
PCISTS
RID
PCI Command
PCI Status
R/W, RO
0280h
R/WC, RO
Revision ID
See description RO
0805h RO
See description RO
0Ah–0Bh
2Ch–2Fh
CC
Class Codes
SS
Subsystem Identifiers
NOTE: Address locations that are not shown should be treated as Reserved.
7.2.1
VID—Identification Register
Offset:
Default Value:
00h–01h
8086h
Attribute:
Size:
RO
16 bits
Default
Bit
and
Description
Access
8086h
RO
15:0
Vendor ID (VID): PCI standard identification for Intel.
82
Datasheet
INTEL [ INTEL ]
