Host Bridge (D0:F0)
7 Host Bridge (D0:F0)
7.1
Functional Description
The host bridge logic manages many of the Intel® SCH central functions most
specifically the FSB controller, memory controller, and thermal and power
management.
The host bridge contains all the registers necessary to configure these functions. These
registers are organized into two groups, each with its own method of access:
1. PCI configuration space. These registers are accessed using the standard PCI cycle
methodology.
2. Custom register space. These registers are accessed through two specific PCI
configuration registers, and they are used to issue messages onto the Intel® SCH
internal message network.
7.1.1
7.1.2
Dynamic Bus Inversion
When the processor or the Intel® SCH drives data, each 16-bit segment is analyzed. If
more than 8 of the 16 signals would normally be driven low on the bus the
corresponding H_DINV# signal will be asserted and the data will be inverted prior to
being driven on the bus. Conversely, whenever the processor or the Intel® SCH
receives data, it monitors H_DINV[3:0]# to determine if the corresponding data
segment should be inverted.
FSB Interrupt Overview
The processor supports FSB interrupt delivery. It does not support the APIC serial bus
interrupt delivery mechanism. Interrupt-related messages are encoded on the FSB as
“Interrupt Message Transactions”. FSB interrupts may originate from a device part of,
or attached to, the Intel® SCH, such as a USB controller or the Intel Graphics Media
Accelerator 500. In such a case the Intel® SCH drives the “Interrupt Message
Transaction” onto the FSB.
In the IOxAPIC environment, an interrupt is generated from the Intel® SCH IOxAPIC to
the processor in the form of a Memory Write to the FSB. Furthermore, the PCI 2.3
specification and PCI Express specification define MSIs (Message Signaled Interrupts)
that also take the form of Memory Writes. MSI-capable devices, such as PCI Express or
USB, may generate an interrupt using the MSI mechanism, writing the interrupt
message directly to the FSB. Alternatively, an Interrupt Message Transaction can be
directed to the IOxAPIC which in turn routes the interrupt message to the FSB using
the traditional IOxAPIC interrupt Memory Write method. The target of an MSI
transaction is dependent upon the target address of the interrupt Memory Write.
Caution:
Improperly formed MSIs, including any non-DWord writes to the space reserved for
MSI, may cause unexpected system behavior.
Datasheet
81
INTEL [ INTEL ]
