Register and Memory Mapping
5.5.3
CONFIG_ADDRESS—Configuration Address Register
I/O Offset (Port):
Default Value:
0CF8h
00000000h
Attribute:
Size:
RO, R/W
32 bits
CONFIG_ADDRESS is a 32-bit register that can be accessed only as a DW. A Byte or
Word reference will pass through the Configuration Address Register and onto the
internal Intel® SCH backbone as an I/O cycle. The CONFIG_ADDRESS register contains
the Bus Number, Device Number, Function Number, and Register Number for which a
subsequent configuration access is intended.
Access
Bit
and
Description
Default
Configuration Enable (CFGE):
R/W
0b
31
0 = Disable accesses to PCI configuration space.
1 = Enable accesses to PCI configuration space.
RO
30:24
Reserved
00h
Bus Number: If the Bus Number is programmed to 00h the target of the
Configuration Cycle is a PCI Bus 0 agent. If this is the case and the
Intel® SCH is not the target (i.e., the device number is ≥3 and not equal
to 7), then a Type 0 Configuration Cycle is generated.
R/W
00h
If the Bus Number is non-zero, and does not fall within the ranges
enumerated by Device 1’s Secondary Bus Number or Subordinate Bus
Number Register, then a Type 1 Configuration Cycle is generated.
23:16
This field is mapped to Byte 8 [7:0] of the request header format during
PCI Express Configuration cycles and A[23:16] during the Type 1
configuration cycles.
Device Number: This field selects one agent on the PCI bus selected by
the Bus Number. When the Bus Number field is “00” the Intel® SCH
decodes the Device Number field. The Intel® SCH is always Device
Number 0 for the Host bridge entity, Device Number 1 for the Host-PCI
Express entity. Therefore, when the Bus Number =0 and the Device
Number equals 0, 1, 2 or 7 the internal Intel® SCH devices are selected.
R/W
00h
15:11
This field is mapped to Byte 6 [7:3] of the request header format during
PCI Configuration cycles.
Function Number: This field allows the configuration registers of a
particular function in a multi-function device to be accessed. The Intel®
SCH ignores configuration cycles to its internal devices if the function
number is not equal to 0 or 1.
R/W
10:8
000b
This field is mapped to Byte 6 [2:0] of the request header format during
PCI Configuration cycles.
Register Number: This field selects one register within a particular Bus,
Device, and Function as specified by the other fields in the Configuration
Address Register.
R/W
00h
7:2
1:0
This field is mapped to Byte 7 [7:2] of the request header format for
during PCI Configuration cycles.
RO
Reserved
00b
68
Datasheet
INTEL [ INTEL ]
