Register and Memory Mapping
The algorithm is as follows:
1. Software copies the contents of the top boot-block to the swap block below it.
2. Software checks that the copy was successful by checksum or other validation
technique.
3. Software sets the TOP_SWAP bit. This will invert A16 for cycles going to the
Firmware Hub and force the processor to read from the swapped block location.
(processor access to FFFF0000h through FFFFFFFFh will be directed to FFFE0000h
through FFFEFFFFh in the Firmware Hub.)
4. Software erases the top block.
5. Software writes the new top block.
6. Software validates the new top block is correct.
7. Software clears the TOP_SWAP bit allowing normal processor access to the top
block address range (FFFF0000h through FFFFFFFFh).
8. Software sets the Top_Swap Lock-Down bit.
If a power failure occurs at any point after step 3, the system will be able to boot from
the copy of the boot block that is stored in the block below the top. This is because a
copy of the TOP_SWAP bit is stored in the RTC well.
Note:
The top-block swap mode may be forced by an external strapping option. When top-
block swap mode is forced in this manner, the TOP_SWAP bit cannot be cleared by
software.
System Management Mode (SMM) uses main memory for System Management RAM
(SMM RAM). SMM uses either a 1-MB, 2-MB, or 8-MB memory region located at the Top
of Memory Segment (TSEG) in main memory (above the 1-MB boundary). This memory
segment in RAM is available for the SMI handlers and code and data storage, and it is
normally hidden from the system OS so that the processor has immediate access to
this memory space upon entry to SMM. The TSEG area can be mapped to any address
within the 32-bit address range.
For more details on the location and size of the SMM memory areas, refer to Table 10
or the Host SMM Control (HSMMCTL) Register definition later in this chapter.
Note:
Other Intel® SCH bus masters are not allowed to access the SMM space.
5.3.11
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into Intel® SCH DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. Processor FSB transactions
are routed accordingly.
5.3.12
Locked Transactions
Only locked cycles to DRAM are supported by the Intel® SCH. Locked cycles to non-
DRAM space are unsupported in the Intel® SCH. This includes all non-physical DRAM
address spaces including peripheral device memory, VGA memory, memory-mapped
I/O, and other memory spaces besides standard DRAM.
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Datasheet
INTEL [ INTEL ]
