Register and Memory Mapping
5.4
I/O Address Space
The I/O map is divided into fixed ranges and variable ranges. Fixed ranges cannot be
moved, but in some cases can be disabled. Variable ranges can be both moved and
disabled.
5.4.1
Fixed I/O Decode Ranges
Table 12 shows the fixed I/O decode ranges from the processor. For each port there
may be separate behavior for reads and writes. Processor cycles that go to reserved
ranges are internally aborted; if the cycle was a read, all 1s will be returned to the
processor.
Table 12.
Fixed I/O Decode Ranges (Sheet 1 of 2)
Port
Size
Read Target
Write Target
Can Disable?
No
Number (Bytes)
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
43h
50h
53h
61h
63h
65h
67h
70h
71h
72h
73h
74h
75h
76h
77h
84h
88h
8Ch
2
2
2
2
2
2
2
2
3
1
3
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
3
8259 Master
8259 Master
8259 Master
8259 Master
8259 Master
8259 Master
8259 Master
8259 Master
8254
8259 Master
8259 Master
8259 Master
8259 Master
8259 Master
8259 Master
8259 Master
8259 Master
8254
No
No
No
No
No
No
No
No
None
8254
No
8254
8254
No
None
8254
No
NMI Controller
NMI Controller
NMI Controller
NMI Controller
None
NMI Controller1
NMI Controller1
NMI Controller1
NMI Controller1
NMI and RTC
RTC
No
Yes, alias to 61h
Yes, alias to 61h
Yes, alias to 61h
No
RTC
No
RTC
NMI and RTC
RTC
Yes, w/ 73h
RTC
Yes, w/ 72h
RTC
NMI and RTC
RTC
No
No
No
No
No
No
No
RTC
RTC
NMI and RTC
RTC
RTC
Internal
Internal/LPC
Internal/LPC
Internal/LPC
Internal
Internal
Datasheet
65
INTEL [ INTEL ]
