Register and Memory Mapping
Table 12.
Fixed I/O Decode Ranges (Sheet 2 of 2)
Port
Size
Read Target
Write Target
Can Disable?
Number (Bytes)
A0h
A4h
2
2
2
2
2
2
2
2
2
8
8
1
1
4
4
8259 Slave
8259 Slave
8259 Slave
8259 Slave
8259 Slave
8259 Slave
8259 Slave
8259 Slave
8259 Slave
8259 Slave
No
No
No
No
No
A8h
ACh
B0h
B2h
Power Management Power Management No
B4h
8259 Slave
8259 Slave
8259 Slave
PATA
8259 Slave
8259 Slave
8259 Slave
PATA
No
No
No
No
No
No
No
No
No
B8h
BCh
170h
1F0h
376h
3F6h
CF8h
CFCh
PATA
PATA
PATA
PATA
PATA
PATA
Internal
Internal
Internal
Internal
NOTE:
1.
Only if the Port 61 Alias-Enable bit (GCS.P61AE) is set—otherwise, none.
5.4.2
Variable I/O Decode Ranges
Table 13 shows the Variable I/O Decode Ranges. They are set using Base Address
Registers (BARs) or other configuration bits in the various configuration spaces. The
PnP software (PCI or ACPI) can use its configuration mechanism to set and adjust these
values. These values should not be mapped on top of fixed address ranges as
unpredictable behavior will result.
f
Table 13.
Variable I/O Decode Ranges
Size
Range Name
Mappable
Target
(Bytes)
ACPI
Anywhere in 64-K I/O Space
64
16
32
64
32
32
32
Power Management
PATA
Bus Master IDE Anywhere in 64-K I/O Space
SMBus
GPIO
Anywhere in 64-K I/O Space
Anywhere in 64-K I/O space
Anywhere in 64-K I/O Space
Anywhere in 64-K I/O Space
Anywhere in 64-K I/O Space
SMB Unit
GPIO Unit
USB 1
USB 2
USB 3
UHCI Host Controller 1
UHCI Host Controller 2
UHCI Host Controller 3
66
Datasheet
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