General Chipset Configuration
6 General Chipset Configuration
This chapter lists the core registers used to configure the Intel® SCH chipset. These
registers are not specific to any particular interface or PCI configuration space, so they
are documented here.
There are four groups of registers that meet this description:
• Root complex topology capability
• Interrupt pin and route definitions
• General configuration
The start and end address offsets listed in the following sections are relative to the Root
Complex Base Address.
6.1
Root Complex Capability
The root complex is used by PCI Express aware operating systems to identify PCI
Express capabilities. It indicates to the OS that the Intel® SCH is capable of
isochronous transfers and that an Intel HD Audio controller exists within the Intel®
SCH.
The following registers follow the PCI Express capability list structure as defined in the
PCI Express specification.
Table 14.
Root Complex Configuration Registers
Address
Symbol
Register Name
0000–0003h RCTCL
0004–0007h ESD
0010–0013h HDD
0014–0017h Reserved
0018–008Fh HDBA
Root Complex Topology Capability List
Element Self Description
Intel® HD Audio Descriptor (Port 15)
Reserved
Intel HD Audio Base Address (Port 15)
Datasheet
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INTEL [ INTEL ]
