Register and Memory Mapping
5.5
I/O Mapped Registers
The Intel® SCH contains two registers that reside in the processor I/O address space −
the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data
(CONFIG_DATA) Register. The Configuration Address Register enables/disables the
configuration space and determines what portion of configuration space is visible
through the Configuration Data window.
5.5.1
NSC—NMI Status and Control Register
I/O Offset (Port):
Default Value:
61h
00h
Attribute:
Size:
RO, R/W
8 bits
Accessand
Default
Bit
Description
SERR# NMI Status (SNS): Set on errors from a PCIe port or internal
functions that generate SERR#. SNE in this register must be cleared in
order for this bit to be set. To reset the interrupt, set Bit 2 to 1 and then
set it to 0.
0
RO
7
IOCHK NMI Status (INS): Set when SERIRQ asserts IOCHK# and INE
in this register is cleared. To reset the interrupt, set Bit 3 to 1 and then
set it to 0.
0
RO
6
5
4
Timer Counter 2 Status (T2S): Reflects the current state of the 8254
Counter 2 output. Counter 2 must be programmed for this bit to have a
determinate value.
0
RO
Refresh Cycle Toggle Status (RTS): This signal toggles from 0 to 1
or 1 to 0 at a rate that is equivalent to when a refresh cycles would
occur.
0
RO
0
R/W
IOCHK NMI Enable (INE): When set, IOCHK# NMIs are disabled and
cleared. When cleared, IOCHK# NMIs are enabled.
3
2
0
R/W
SERR# NMI Enable (SNE): When set, SERR# NMIs are disabled and
cleared. When cleared, SERR# NMIs are enabled.
Speaker Data Enable (SDE): When this bit is a 0, the SPKR output is
a 0. When this bit is a 1, the SPKR output is equivalent to the Counter 2
OUT signal value.
0
R/W
1
0
0
R/W
Timer Counter 2 Enable (TC2E): When cleared, counter 2 counting is
disabled. When set, counting is enabled.
5.5.2
NMIE—NMI Enable Register
I/O Offset (Port):
Default Value:
70h
00h
Attribute:
Size:
R/W
8 bits
Accessand
Default
Bit
Description
NMI Enable (EN):
1 = NMI sources disabled.
0
WO
7
0 = NMI sources enabled.
0
WO
Real Time Clock Index (RIDX): Selects the RTC register or CMOS
RAM address to access.
6:0
Datasheet
67
INTEL [ INTEL ]
