Register and Memory Mapping
5.5.4
RSTC—Reset Control Register
I/O Offset (Port):
Default Value:
0CF9h
00h
Attribute:
Size:
R/W, RO
8 bits
Accessand
Default
Bit
Description
0
RO
7:4
Reserved
Cold Reset (COLD): This bit will cause a cold reset to the platform,
which is performed by driving SLPMODE low, SLPRDY# low, and
RSTRDY# low. In response to this, the platform will perform a full
power cycle.
0
R/W
3
2
1
0
RO
Reserved
Warm Reset (WARM): This bit will cause a warm reset to the
platform, which is performed by driving RSTRDY# low. In response to
this, the platform will drive RESET# low to reset the processor and all
peripherals.
0
R/W
CPU-Only Reset (CPU): This bit causes H_CPURST# to be asserted,
with processor timing requirements met for minimum pulse width. The
processor Power-On-Config register (HPOC) contents will be driven on
the host address bus, and latched on the deassertion edge of
H_CPURST#.
0
R/W
0
5.5.5
CONFIG_DATA—Configuration Data Register
I/O Offset (Port):
Default Value:
0CFCh
00000000h
Attribute:
Size:
R/W
32 bits
CONFIG_DATA is a 32-bit read/write window into configuration space. The portion of
configuration space that is referenced by CONFIG_DATA is determined by the contents
of CONFIG_ADDRESS.
Access and
Default
Bit
Description
Configuration Data Window (CDW): If Bit 31 of the
CONFIG_ADDRESS is 1, any I/O access to the CONFIG_DATA register
will produce a configuration transaction using the contents of
CONFIG_ADDRESS to determine the bus, device, function, and offset
of the register to be accessed.
R/W
31:0
0000 0000h
§ §
Datasheet
69
INTEL [ INTEL ]
