Register and Memory Mapping
5.3.7
Top of Memory Segment (TSEG)
TSEG is a 1-MB, 2-MB, or 8-MB memory region located below Intel Graphics Media
Adapter stolen memory, which is at the top of physical memory (TOM). It is used for
System Management Mode accesses by the processor. See Table 10 for more
information on SMM.
Processor accesses to the TSEG range without SMM attribute or without WB attribute
are forwarded to memory as invalid accesses. Non-SMM-mode Write Back cycles that
target TSEG space are completed to DRAM for cache coherency. The TSEG memory
region is not accessible by non-processor bus masters (that is, PCI Express, USB, etc.)
5.3.8
APIC Configuration Space (FEC00000h – FECFFFFFh)
This range is reserved for APIC configuration space which includes an IOxAPIC and a
Local (processor) APIC. The IOxAPIC is located at the default address FEC00000h to
FEC70FFFh and is part of the LPC bridge controller (Device 31, Function 0). The default
Local APIC configuration space goes from FEC80000h to FECFFFFFh.
Processor accesses to the Local APIC configuration space do not result in external bus
activity since the Local APIC configuration space is internal to the processor. However,
an MTRR must be programmed to make the Local APIC range uncacheable (UC). The
Local APIC base address in each processor should be relocated to the FEC00000h to
FECFFFFFh range so that one MTRR can be programmed to 64 KB for the Local and
IOxAPIC.
5.3.9
High BIOS Area
The top 2 MB (FFC00000h – FFFFFFFFh) of the PCI Memory Address Range is reserved
for System BIOS (High BIOS), extended BIOS for PCI devices. The processor begins
execution from the High BIOS after reset. This region is mapped to the LPC controller
so that the upper subset of this region aliases to the 16-MB through 256-KB range. The
actual address space required for the BIOS is less than 2 MB but the minimum
processor MTRR range for this region is 2 MB so that full 2 MB must be considered.
5.3.10
Boot Block Update
The Intel® SCH supports a Top-Block Swap mode where the top boot block on the
Firmware Hub (FWH) is swapped with a block in a different location. This allows the
boot block to be safely updated while protecting the system from a power loss When
BC.TS is set, the Intel® SCH inverts A16 for cycles going to the upper two 64 KB blocks
in the firmware. When BC.TS is cleared, the Intel® SCH will not invert A16. This bit is
cleared by RTCRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block,
and the block immediately below the top block is reserved for doing boot-block
updates.
Datasheet
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