Register and Memory Mapping
Table 10.
Intel® SCH Memory Map (Sheet 2 of 2)
Starting
Address
Ending
Address
Device
Comment
PCI Configuration Space (2 GB to 4 GB)
IOxAPIC
HPET
FEC00000h
FED00000h
FEFD40000h
FEC00040h
FED003FFh
FED4BFFFh
High Performance Event Timer
LPC
TPM 1.2
LPC, See Note 3 for CMC address
space
High BIOS
FFF80000h
FFFFFFFFh
Configurable Main Memory Configuration Spaces
PCI Express Port 1
Anywhere in 32-bit range
Anywhere in 32-bit range
Anywhere in 32-bit range
Anywhere in 32-bit range
Configured by D30:F0:MBL
Configured by D30:F0:PMBL
Configured by D30:F1:MBl
Configured by D30:F1:PMBL
PCI Express Port 1
(prefetchable)
PCI Express Port 2
PCI Express Port 2
(prefetchable)
Root Complex Base
Register
1 KB anywhere in 32-bit range
1 KB anywhere in 32-bit range
Configured by D30:F0:RCBA
USB2 Host
Controller
Configured by D20:F7:MEM_BASE
Intel HD Audio Host
Controller
512 KB anywhere in 32-bit range Configured by D27:F0:LBAR
SDIO 1
SDIO 2
SDIO 3
1 KB anywhere in 32-bit range
1 KB anywhere in 32-bit range
1 KB anywhere in 32-bit range
Configured by D30:F0:MEM_BASE
Configured by D30:F1:MEM_BASE
Configured by D30:F2:MEM_BASE
NOTES:
1.
All accesses to addresses within the main memory range will be forwarded by the Intel®
SCH to the DRAM unless they fall into one of the optional ranges specified in this section.
Top of Memory is determined by examining the contents of the DRAM Rank Population
register and calculating the total system memory based on the device width, device
density, and number of ranks installed. Up to 2 GB of total system memory is supported.
The Chipset Microcode (CMC) base address locates within the LPC space and consumes
64 KB of space. The starting address for the CMC code can be FFFB0000h, FFFC0000h,
FFFD0000h, or FFFE0000h. Refer to Section 2.17 for selecting the CMC start address.
Make sure to avoid using the same starting address for other LPC devices in the system.
2.
3.
Datasheet
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