Signal Description
Power
Well
Signal Name
Type
Description
Sleep Mode: SLPMODE determines which sleep state
is entered. When SLPMODE is high, S3 will be chosen.
When SLPMODE is low, S4/S5 will be the selected
sleep mode.
O
SLPMODE
Sus
Sus
CMOS3.3
Reset Warning: Asserting the RSTWARN signal tells
the Intel® SCH to enter a sleep state or begin to
power down. A system management controller might
do so after an external event, such as pressing of the
power button or occurrence of a thermal event.
I
RSTWARN
SLPRDY#
CMOS3.3
Sleep Ready: The Intel® SCH will drive the
SLPRDY# signal low to indicate to the system
management controller that the Intel® SCH is awake
and able to placed into a sleep state. deassertion of
this signal indicates that a wake is being requested
from a system device.
O
Sus
CMOS3.3
Reset Ready: Assertion of the RSTRDY# signal
indicates to the system management controller that it
is ready to be placed into a low power state. During a
transition from S0 to S3/4/5 sleep states, the Intel®
SCH asserts RSTRDY# and CPURST# after detecting
assertion of the RSTWARN signal from the external
system management controller.
O
RSTRDY#
GPE#
Sus
Sus
CMOS3.3
General Purpose Event: GPE# is asserted by an
external device (typically, the system management
controller) to log an event in the Intel® SCH ACPI
space and cause an SCI (if enabled).
I
CMOS3.3
_OD
2.12
Real Time Clock Interface
Power
Well
Signal Name
Type
Description
Crystal Input 1: This signal is connected to the
32.768-kHz crystal. If no external crystal is used, then
RTC_X1 can be driven with the desired clock rate.
Special
A
RTC_X1
RTC
Crystal Output 2: This signal is connected to the
32.768-kHz crystal. If no external crystal is used, then
RTC_X2 should be left floating.
Special
A
RTC_X2
RTC
42
Datasheet
INTEL [ INTEL ]
