Signal Description
2.7
Parallel ATA (PATA) Signals
Power
Well
Signal Name
Type
Description
Device Data: These signals drive the corresponding
signals on the PATA connector. There is an internal
13.3-kΩ pull-down on PATA_DD7.
I/O
CMOS3.3-5
PATA_DD[15:0]
Core
Device Address: These output signals are connected
to the corresponding signals on the PATA connectors.
They are used to indicate which byte in either the ATA
command block or control block is being addressed.
O
PATA_DA[2:0]
PATA_DIOR#
Core
Core
CMOS3.3-5
Disk I/O Read (PIO and Non-Ultra DMA): This is
the command to the PATA device that it may drive data
onto the DD lines. Data is latched by the Intel® SCH
on the deassertion edge of PATA_DIOR#. The PATA
device is selected either by the ATA register file chip
selects (PATA_DCS1# or PATA_DCS3#) and the
PATA_DA lines, or the PATA DMA acknowledge
(PATA_DDAK#).
O
CMOS3.3-5
Disk I/O Write (PIO and Non-Ultra DMA): This is
the command to the PATA device that it may latch data
from the PATA_DD lines. Data is latched by the PATA
device on the deassertion edge of PATA_DIOW#. The
PATA device is selected either by the ATA register file
chip selects (PATA_DCS1# or PATA_DCS3#) and the
PATA_DA lines, or the PATA DMA acknowledge
(PATA_DDAK#).
O
PATA_DIOW#
PATA_DDACK#
Core
Core
CMOS3.3-5
Device DMA Acknowledge: This signal directly
drives the DAK# signals on the PATA connectors. Each
is asserted by the Intel® SCH to indicate to PATA DMA
slave devices that a given data transfer cycle
(assertion of PATA_DIOR# or PATA_DIOW#) is a DMA
data transfer cycle. This signal is used in conjunction
with the PCI bus master PATA function and are not
associated with any AT-compatible DMA channel.
O
CMOS3.3-5
Device Chip Select for 300 Range: This chip select
is for the ATA control register block. This signal is
connected to the corresponding signal on the
connector.
O
PATA_DCS3#
PATA_DCS1#
Core
Core
CMOS3.3-5
Device Chip Selects for 100 Range: This chip select
is for the ATA command register block. This signal is
connected to the corresponding signal on the PATA
connector.
O
CMOS3.3-5
Device DMA Request: This input signal is directly
driven from the DRQ signals on the PATA connector. It
is asserted by the PATA device to request a data
transfer, and used in conjunction with the PCI bus
master PATA function and are not associated with any
AT-compatible DMA channel. There is an internal
13.3 kΩ pull-down on this pin.
I
PATA_DDREQ
PATA_IORDY
Core
Core
CMOS3.3-5
I/O Channel Ready (PIO): This signal will keep the
strobe active (PATA_DIOR# on reads, PATA_DIOW# on
writes) longer than the minimum width. It adds wait
states to PIO transfers.
I
CMOS3.3-5
38
Datasheet
INTEL [ INTEL ]
