Signal Description
mismatch between the die-to-package interface. If cracking between the die-to-package
interface occurs, product performance or reliability is not affected.
2.17
Functional Straps
The following signals are used to configure certain Intel® SCH features. All strap
signals are in the core power well. They are sampled at the rising edge of PWROK and
then revert later to their normal usage. Straps should be driven to the desired state at
least four LPC (PCI) clocks prior to the rising edge of PWROK.
Table 3.
Functional Strap Definitions
Signal Name
Strap Function
Comments
BSEL2: Selects the frequency of the host interface
and DDR interface. Normal system configuration will
have this signal connected to the processor’s BSEL2
signal and will not require external pull-up/pull-
down resistors.
CFG[1:0]: Selects the frequency of the internal
graphics device.
FSB/DDR Frequency
Select
BSEL2
CFG[1:0]
Graphics Frequency
Select
BSEL2
CFG1
CFG0
FSB Freq
GFX Freq
1
0
0
0
0
0
0
0
1
100 MHz
133 MHz
133 MHz
200 MHz
266 MHz
200 MHz
All other combinations are reserved
Selects the starting address that the CMC will use to
start fetching code (GPIO3 is the most significant).
GPIO3
GPIO0
CMC Base Address
CMC (Chipset
Microcode) Base
Address
GPIO3
GPIO0
0
0
0
1
FFFB0000h
FFFC0000h
FFFD0000h
(default)
1
1
0
1
FFFE0000h
Selects the drive strength of the LPC_CLKOUT0
clock.
LPC_CLKOUT[0]
Buffer Strength
RESERVED1
XOR_TEST
0 = 1 Load driver strength
1 = 2 Load driver strength
Enables XOR chain mode
0 = XOR mode enable
1 = XOR mode disable (default)
XOR Chain Enable
NOTE: XOR_TEST includes an internal pullup
resistor.
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46
Datasheet
INTEL [ INTEL ]
