Signal Description
Power
Well
Signal Name
Type
Description
I
IDE Interrupt: Input from the PATA device indicating
request for an interrupt. Tied internally to IRQ14.
PATA_IDEIRQ
Core
CMOS3.3-5
2.8
Intel HD Audio Interface
Power
Well
Signal Name
Type
Description
O
Intel® HD Audio Reset: This signal is the reset to
external Codecs
HDA_RST#
Core
CMOS_HDA
Intel HD Audio Sync: This signal is an 48-kHz fixed
rate sample sync to the Codec(s). It is also used to
encode the stream number.
O
HDA_SYNC
HDA_CLK
Core
Core
CMOS_HDA
Intel HD Audio Clock (Output): This signal is a
24.000-MHz serial data clock generated by the Intel
HD Audio controller. This signal contains an
integrated pull-down resistor so that it does not float
when an Intel HD Audio CODEC (or no CODEC) is
connected.
O
CMOS_HDA
Intel HD Audio Serial Data Out: This signal is a
serial TDM data output to the Codec(s). The serial
output is double-pumped for a bit rate of 48 MB/s for
HD Audio.
O
HDA_SDO
Core
Core
CMOS_HDA
Intel HD Audio Serial Data In: These serial inputs
are single-pumped for a bit rate of 24 MB/s. They
have integrated pull-down resistors that are always
enabled.
I
HDA_SDI[1:0]
CMOS_HDA
Intel HD Audio Dock Enable: This active low signal
controls the external Intel HD Audio docking isolation
logic. When deasserted, the external docking switch
is in isolate mode. When asserted, the external
docking switch electrically connects the Intel HD
Audio dock signals to the corresponding Intel SCH
signals.
O
HDA_DOCKEN#
HDA_DOCKRST#
Core
Core
CMOS_HDA
Intel HD Audio Dock Reset: This signal is a
dedicated reset signal for the codec(s) in the docking
station. It works similar to, but independent of, the
normal HDA_RST# signal.
O
CMOS_HDA
Datasheet
39
INTEL [ INTEL ]
