Signal Description
2.13
JTAG Interface
The JTAG interface is accessible only after PWROK is asserted.
Power
Well
Signal Name
Type
Description
JTAG Test Clock: TCK is a clock input used to drive
Test Access Port (TAP) state machine during test and
debugging. This input may change asynchronous to the
host clock.
I
TCK
Sus
CMOS
I
JTAG Test Data In: TDI is used to serially shift data
and instructions into the TAP.
TDI
Sus
Sus
Sus
Sus
CMOS
O
JTAG Test Data Out: TDO is used to serially shift data
out of the device.
TDO
TMS
CMOS_OD
I
Test Mode Select: This signal is used to control the
state of the TAP controller.
CMOS
I
Test Reset: This signal resets the controller logic. It
should be pulled down unless TCK is active.
TRST#
CMOS
2.14
Miscellaneous Signals and Clocks
Power
Well
Signal Name
Type
Description
DA_REFCLKINP/
DA_REFCLKINN
Display PLLA CLK Differential Pair: 96 MHz, no
SSC support.
I
I
Core
DB_REFCLKINPSSC/
DB_REFCLKINNSSC
Display PLLB CLK Differential Pair: display PLL
differential clock pair for super SSC.
Core
Core
O
Clock Required: The Intel® SCH will not de-assert
CLKREQ# and will not thus enable a power
management mode to the clock chip.
CLKREQ#
CLK14
CMOS3.3
_OD
Oscillator Clock: This signal is used for 8254 timers
and HPET. It runs at 14.31818 MHz. This clock stops
(and should be low) during S3, S4, and S5 states.
CLK14 must be accurate to within 500 ppm over
100 µs (and longer periods) to meet HPET accuracy
requirements.
I
Core
RTC
CMOS3.3
Internal VRM Enable: This signal is used to enable
or disable the integrated 1.5-V Voltage Regulators
for the Suspend and Auxiliary wells on the Intel®
SCH. When connected to VSS, the VRMs are
disabled; when connected to the RTC power well, the
VRMs are enabled. This signal is in the RTC well. It is
not latched and must remain valid for the VRMs to
behave properly.
I
INTVRMEN
CMOS3.3
Speaker: The SPKR signal is the output of counter 2
and is internally ANDed with Port 61h bit 1 to
provide Speaker Data Enable. This signal drives an
external speaker driver device, which in turn drives
the system speaker. Upon SLPMODE, its output state
is 0.
O
SPKR
Core
CMOS3.3
Datasheet
43
INTEL [ INTEL ]
