Signal Description
2.9
LPC Interface
Power
Well
Signal Name
Type
Description
I/O
CMOS3.3
LPC Address/Data: Multiplexed Command, Address,
Data
LPC_AD[3:0]
LPC_FRAME#
LPC_SERIRQ
Core
Core
Core
O
LPC Frame: This signal indicates the start of an LPC/
FHW cycle.
CMOS3.3
I/O
CMOS3.3
Serial Interrupt Request: This signal conveys the
serial interrupt protocol.
Clock Run: This signal gates the operation of the
LPC_CLKOUTx. Once an interrupt sequence has
started, LPC_CLKRUN# should remain asserted to
allow the LPC_CLKOUTx to run.
I/O
CMOS3.3
LPC_CLKRUN#
Core
Core
LPC Clock: These signals are the clocks driven by the
Intel® SCH to LPC devices. Each clock can support up
to two loads.
O
LPC_CLKOUT[2:0]
CMOS3.3
NOTE: The primary boot device like FWH and SPI
(behind SMC) should be connected to
LPC_CLKOUT[0]
2.10
SMBus Interface
Power
Well
Signal Name
Type
Description
I/O
CMOS3.3
_OD
SMBus Data: This signal is the SMBus data pin. An
external pull-up resistor is required.
SMB_DATA
Core
Core
Core
I/O
CMOS3.3
_OD
SMBus Clock: This signal is the SMBus clock pin. An
external pull-up resistor is required.
SMB_CLK
I
SMBus Alert: This signal can be used to generate an
SMI#.
SMB_ALERT#
CMOS3.3
_OD
40
Datasheet
INTEL [ INTEL ]
