Signal Description
2.11
Power Management Interface
Power
Well
Signal Name
Type
Description
Thermal Alarm: This signal is an active low signal
generated by external hardware to generate an SMI
or SCI.
I
THRM#
Core
DDR
RTC
CMOS3.3
I
System Reset: This signal forces a reset after being
de-bounced. This signal is powered by VCCSM.
RESET#
PWROK
CMOS3.3
Power OK: When asserted, PWROK is an indication
to the Intel® SCH that core power is stable. PWROK
can be driven asynchronously.
I
CMOS3.3
Resume Well Reset: This signal is used for resetting
the resume well. An external RC circuit is required to
ensure that the resume well power is valid prior to
RSMRST# going high.
I
RSMRST#
RTC
CMOS3.3
RTC Well Reset: This signal is normally held high (to
V
CC_RTC), but can be driven low on the motherboard
to test the RTC power well and reset some bits in the
RTC well registers that are otherwise not reset by
SLPMODE or RSMRST#. An external RC circuit on the
RTCRST# signal creates a time delay such that
RTCRST# will go high some time after the battery
voltage is valid. This allows the Intel® SCH to detect
when a new battery has been installed. The RTCRST#
input must always be high when other non-RTC power
planes are on.
I
RTCRST#
RTC
CMOS3.3
NOTE: Unlike many previous products, the Intel®
SCH does not use RTCRST# to clear CMOS. RTCRST#
does not set a bit which BIOS can then read as a
directive to clear CMOS.
This signal is in the RTC power well.
Suspend Clock: This signal is an output of the RTC
generator circuit (32.768 kHz). SUSCLK can have a
duty cycle from 30% to 70%.
O
SUSCLK
WAKE#
Sus
Sus
CMOS3.3
I
PCI Express* Wake Event: This signal indicates a
PCI Express port wants to wake the system.
CMOS3.3
Stop CPU Clock: This signal is used to support the
C3 state. Asserting this signal halts the clocks to the
processor by controlling the enable of the clock chip.
O
STPCPU#
Core
CMOS3.3
Deeper Sleep Voltage Regulator: This signal is
asserted by the Intel® SCH to the processors voltage
regulator. When the signal is high, the voltage
regulator outputs the lower “Deeper Sleep” voltage.
When the signal is low (default), the voltage regulator
outputs the higher “Normal” voltage.
O
DPRSLPVR
SLPIOVR#
Core
Core
CMOS3.3
This signal is in the core I/O plane and has a standard
CMOS output (not open drain).
Sleep I/O Voltage Regulator Disable: The
SLPIOVR# can be connected to an external VR and be
used to control power supplied to the processors I/O
rail in the C6 state.
O
CMOS3.3
Datasheet
41
INTEL [ INTEL ]
