Signal Description
2.4
Universal Serial Bus (USB) Signals
Power
Well
Signal Name
Type
Description
USB Port 5:0 Differentials: Bus Data/Address/
Command Bus: These differential pairs are used to
transmit data/address/command signals for Ports 0
through 5. These ports can be routed to either the EHCI
controller or one of the three UHCI controllers and are
capable of running at either high-, full-, or low-speed.
USB_DP[5:0]/
USB_DN[5:0]
I/O
USB
Sus
USB Port 7:6 Differentials: Bus Data/Address/
Command Bus: These differential pairs are used to
transmit data/address/command signals for Ports 6 and
7. These ports are routed only to the EHCI controller and
should be used ONLY for in-system USB 2.0 devices.
USB_DP[7:6]/
USB_DN[7:6]
I/O
USB
Sus
Resistor Bias P: This pin is an analog connection point
for an external resistor. This signal is used to set
transmit currents and internal load resistors.
O
A
USB_RBIASP
USB_RBIASN
USB_CLK48
Sus
Sus
Sus
Resistor Bias N: This pin is an analog connection point
for an external resistor. This signal is used to set
transmit currents and internal load resistors.
I
A
48-MHz Clock: This optional clock is used to run the
USB controller. By default, the Intel® SCH uses
DA_REFCLKIN to clock the USB logic.
I
USB
Overcurrent Indicators: These signals set
corresponding bits in the USB controllers to indicate that
an overcurrent condition has occurred.
I
USB_OC[7:0]#
Sus
Sus
CMOS3.3
NOTE: USB_OC[7:0]# are not 5-V tolerant.
USB Client Connect: This signal, on GPIOSUS3, may
be used in systems where USB port 2 is configured for
client mode. This indicates connection to an external
USB host has been established.
USBCC/
GPIOSUS3
I/O
CMOS3.3
NOTE: If USB Client support is enabled, then this signal
is dedicated for USB Client Connect.
2.5
PCI Express* Signals
Power
Well
Signal Name
Type
Description
PCIE_PETp[2:1]
PCIE_PETn[2:1]
O
PCIE
PCI Express Transmit: PCIE_PETp[2:1] are PCI
Express Ports 2:1 transmit pair (P and N) signals.
Core
PCIE_PERp[2:1]
PCIE_PERn[2:1]
I
PCI Express Receive: PCIE_PERp[2:1] PCI Express
Ports 2:1 receive pair (P and N) signals.
Core
Core
PCIE
PCIE_CLKINP
PCIE_CLKINN
I
PCI Express Input Clock: 100-MHz differential clock
signals.
PCIE
PCI Express Compensation Pin: Output
compensation for both current and resistance. Also for
LVDS and SDVO interfaces.
I/O
A
PCIE_ICOMPO
PCIE_ICOMPI
Core
Core
I/O
A
PCI Express Compensation Pin: Input compensation
for current. Also for LVDS and SDVO interfaces.
36
Datasheet
INTEL [ INTEL ]
