Signal Description
Power
Well
Signal Name
Type
Description
Serial Digital Video TV-OUT Synchronization
Clock: Differential clock pair that is driven by the SDVO
device to the Intel® SCH. If SDVO_TVCLKIN[±] is
used, it becomes the frequency reference for the Intel®
SCH dot clock PLL, but will be driven back to the SDVO
device through the SDVOB_CLK[±] differential pair.
SDVO_TVCLKIN+
SDVO_TVCLKIN-
I
Core
PCIE
This signal pair has an operating range of
100–200 MHz, so if the desired display frequency is less
than 100 MHz, the SDVO device must apply a multiplier
to get the SDVO_TVCLKIN[±] frequency into the
100- to 200-MHz range.
Serial Digital Video Field Stall: Differential input pair
that allows a scaling SDVO device to stall the Intel®
SCH pixel pipeline.
SDVO_STALL+
SDVO_STALL-
I
Core
Core
PCIE
SDVO Control Clock: Single-ended control clock line
from the Intel® SCH to the SDVO device. Similar to I2C
clock functionality, but may run at faster frequencies.
SDVO_CTRLCLK is used in conjunction with
SDVO_CTRLDATA to transfer device config, PROM, and
monitor DDC information. This interface directly
connects the Intel® SCH to the SDVO device.
I/O
CMOS3.3
_OD
SDVO_CTRLCLK
SDVO Control Data: SDVO_CTRLDATA is used in
conjunction with SDVO_CTRLCLK to transfer device
config, PROM, and monitor DDC information. This
interface directly connects the Intel® SCH to the SDVO
device.
I/O
SDVO_CTRLDATA CMOS3.3
_OD
Core
2.3.3
Display Data Channel (DDC) and GMBus Support
Power
Well
Signal Name
Type
Description
I/O
CMOS3.3
_OD
Display Data Channel Clock: I2C-based control signal
(Clock) for EDID control.
L_DDC_CLK
Core
I/O
CMOS3.3
_OD
Display Data Channel Data: I2C-based control signal
(Data) for EDID control.
L_DDC_DATA
L_CTLA_CLK
L_CTLB_DATA
Core
Core
Core
I/O
CMOS3.3
_OD
Control A Clock: This signal can be used to control
external clock chip for SSC - optional.
I/O
CMOS3.3
_OD
Control B Data: This signal can be used to control
external clock chip for SSC – optional.
O
L_VDDEN
L_BKLTEN
L_BKLTCTL
Core
Core
Core
LCD Power Enable: Panel power enable control.
CMOS3.3
O
LCD Backlight Enable: Panel backlight enable control.
CMOS3.3
O
LCD Backlight Control: This signal allows control of
LCD brightness.
CMOS3.3
Datasheet
35
INTEL [ INTEL ]
