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319537-003US 参数 Datasheet PDF下载

319537-003US图片预览
型号: 319537-003US
PDF下载: 下载PDF文件 查看货源
内容描述: 英特尔系统控制器中心 [Intel System Controller Hub]
分类和应用: 控制器
文件页数/大小: 450 页 / 2593 K
品牌: INTEL [ INTEL ]
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Signal Description  
2.3  
Integrated Display Interfaces  
2.3.1  
LVDS Signals  
Power  
Well  
Signal  
Type  
Description  
LA_DATAP[3:0]  
LA_DATAN[3:0]  
O
LVDS  
Channel A Differential Data Output: Differential  
signal pair.  
Core  
LA_CLKP  
LA_CLKN  
O
LVDS  
Channel A Differential Clock Output: Differential  
signal pair.  
Core  
2.3.2  
Serial Digital Video Output (SDVO) Signals  
Power  
Well  
Signal Name  
Type  
Description  
Serial Digital Video Channel B Red: SDVOB_RED[±]  
is a differential data pair that provides red pixel data for  
the SDVOB channel during Active periods. During  
blanking periods it may provide additional such as sync  
information, auxiliary configuration data, etc. This data  
pair must be sampled with respect to the  
SDVOB_RED+  
SDVOB_RED-  
O
PCIE  
Core  
SDVOB_CLK[±] signal pair.  
Serial Digital Video Channel B Green:  
SDVOB_GREEN[±] is a differential data pair that  
provides green pixel data for the SDVOB channel during  
Active periods. During blanking periods it may provide  
additional such as sync information, auxiliary  
configuration data, etc. This data pair must be sampled  
with respect to the SDVOB_CLK[±] signal pair.  
SDVOB_GREEN+  
SDVOB_GREEN-  
O
PCIE  
Core  
Core  
Serial Digital Video Channel B Blue:  
SDVOB_BLUE[±] is a differential data pair that provides  
blue pixel data for the SDVOB channel during Active  
periods. During blanking periods it may provide  
additional such as sync information, auxiliary  
configuration data, etc. This data pair must be sampled  
with respect to the SDVOB_CLK[±] signal pair.  
SDVOB_BLUE+  
SDVOB_BLUE-  
O
PCIE  
Serial Digital Video Channel B Clock: This  
differential clock signal pair is generated by the Intel®  
SCH internal PLL and runs between 100 MHz and  
200 MHz.  
SDVOB_CLK+  
SDVOB_CLK-  
O
PCIE  
Core  
Core  
If TV-out mode is used, the SDVO_TVCLKIN[±] clock  
input is used as the frequency reference for the PLL.  
The SDVOB_CLK[±] output pair is then driven back to  
the SDVO device.  
Serial Digital Video Input Interrupt: Differential  
input pair that may be used as an interrupt notification  
from the SDVO device to the Intel® SCH. This signal  
pair can be used to monitor hot plug attach/detach  
notifications for a monitor driven by an SDVO device.  
SDVOB_INT+  
SDVOB_INT-  
I
PCIE  
34  
Datasheet  
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