Signal Description
Power
Well
Signal
Type
Description
Deep Sleep: This signal is asserted by the Intel® SCH to
the processor. When the signal is low, the processor enters
the Deep Sleep state by gating off the processor Core clock
inside the processor. When the signal is high (default), the
processor is not in the Deep Sleep state. This signal and the
H_STPCLK# pin shut the clock in the processor and at the
clock generator, respectively. The H_DPSLP# assertion time
is wider than the H_STPCLK# assertion time in order for
the processor to receive an active clock input whenever
H_DPSLP# is deasserted.
O
CMOS
H_DPSLP#
Core
Deeper Sleep: When asserted on the platform, this signal
causes the processor to transition from the Deep Sleep
State to the Deeper Sleep state. To return to the deep sleep
state, H_DPRSTP# must be deasserted.
O
CMOS
H_DPRSTP#
Core
Core
CPU Power Good: This signal is used for Enhanced Intel
SpeedStep® Technology support. H_CPUPWRGD goes to
the processor. It is kept high during the Enhanced Intel
SpeedStep® Technology state transition to prevent loss of
processor context.
O
CMOS
H_CPUPWRGD
Host Interface Reference and Compensation
Differential clock Input for the Host PLL: This low-
I
H_CLKINP
H_CLKINN
voltage differential signal pair is used for FSB transactions.
The clock input also supplies a signal to the internal core
and memory interface clocks.
CMOS
0.8
Core
Host Resistor Compensation: This is connected to a
reference resistor to dynamically calibrate the driver
strengths.
I/O
A
H_RCOMPO
H_SWING
Core
Core
Core
I
A
Voltage Swing Calibration
Voltage Reference: These pins are for the input buffer
differential amplifier to determine a high versus a low input
voltage.
H_GVREF
H_CGVREF
I
A
2.2
System Memory Signals
Power
Well
Signal
Type
Description
I/O
CMOS1.8
Data Lines: The SM_DQ[63:0] signals interface to the
DRAM data bus.
SM_DQ[63:0]
DDR
Data Strobes: These signals are the data strobes used
for capturing data. Each strobe signal corresponds to 8
data bits. During writes, SM_DQSx is centered in data.
During reads, SM_DQSx is edge aligned with data.
I/O
CMOS1.8
SM_DQS[7:0]
SM_MA[14:0]
DDR
DDR
O
Memory Address: These signals are used to provide
the multiplexed row and column address to the SDRAM.
CMOS1.8
32
Datasheet
INTEL [ INTEL ]
