Signal Description
Power
Well
Signal
Type
Description
Bank Select (Bank Address): These signals define
which banks are selected within each SDRAM row. Bank
select and memory address signals combine to address
every possible location within an SDRAM device.
O
SM_BS[2:0]
DDR
DDR
CMOS1.8
Row Address Strobe: SM_RAS# is used to signify the
presence of the row address on SM_MA to the DRAM
device being selected.
O
SM_RAS#
CMOS1.8
Column Address Strobe: SM_CAS# is used to signify
the presence of the column address on SM_MA to the
DRAM device being selected.
O
SM_CAS#
SM_WE#
DDR
DDR
CMOS1.8
O
Write Enable: SM_WE# tells the DRAM memory that it
is performing a write operation on the bus.
CMOS1.8
Receive Enable In: This signal connects to
SM_SRCVENOUT# internally. This input (driven from
SM_SRCVENOUT#) enables the DQS input buffers
during reads.
I
SM_RCVENIN#
DDR
DDR
CMOS1.8
Receive Enable Out: This signal connects to
SM_SRCVENIN# internally. It is part of the feedback
used to enable the DQS input buffers during reads.
O
SM_RCVENOUT#
CMOS1.8
Differential DDR Clock: SM_CKx and SM_CKx# pairs
are differential clock outputs. The crossing of the
positive edge of SM_CKx and the negative edge of
SM_CKx# is used to sample the address and control
signals on the DRAM.
SM_CK[1:0]
SM_CK[1:0]#
O
DDR
DDR
CMOS1.8
Chip Select: These signals select particular DRAM
components during the active state. There is one
SM_CSx# for each DRAM rank, toggled on the positive
edge of SM_CKx.
O
SM_CS[1:0]#
SM_CKE[1:0]
CMOS1.8
Clock Enable: SM_CKEx is used to initialize DRAM
during power-up and to place all DRAM rows into and
out of self-refresh during the S3 Suspend-to-RAM low
power state. SM_CKEx is also used to dynamically
power down inactive DRAM rows. There is one
SM_CKEx per SDRAM row, toggled on the positive edge
of SM_CKx.
O
DDR
CMOS1.8
Input Buffer VREF: This signal is for the input buffer
differential amplifier to determine a high versus a low
input voltage.
I
A
SM_VREF
DDR
DDR
Resistor Compensation Output Pin: This pin is
connected to a reference resistor to dynamically
calibrate the driver strengths.
I/O
A
SM_RCOMPO
Datasheet
33
INTEL [ INTEL ]
