Signal Description
Power
Well
Signal
Type
Description
Response Signals: These signals indicate the type of
response as shown below:
000 = Idle State
001 = Retry Response
010 = Deferred Response
011 = Reserved (not driven by Intel® SCH)
100 = Hard Failure (not driven by Intel® SCH)
101 = No data response
O
H_RS[2:0]#
Core
AGTL+
110 = Implicit Writeback
111 = Normal data response
Thermal Trip: When low, this signal indicates that a
thermal trip from the processor occurred, and corrective
action will be taken.
I
H_THRMTRIP#
H_CPUSLP#
H_PBE#
Core
Core
Core
CMOS
CPU SLP: This signal puts the processor into a state that
saves power vs. the Stop-Grant state. However, during that
time, no snoops occur. It will go active for all other sleep
states.
O
CMOS
Pending Break Event: This signal can be used in some
states for notification by the processor of pending interrupt
events.
I
CMOS
Initialization: The Intel® SCH can be configured to
support a special meaning to the processor during
H_CPURST# deassertion. H_INIT# functionality for
resetting the processor is not supported. This signal
requires a board-level pull-up.
O
CMOS
_OD
H_INIT#
H_INTR
Core
Core
Core
Core
Core
Processor Interrupt: H_INTR is asserted by the Intel®
SCH to signal the processor that an interrupt request is
pending and needs to be serviced. It is an asynchronous
output normally driven low.
O
CMOS
Non-Maskable Interrupt: The H_NMI is used to force a
non-maskable interrupt to the processor. The processor
detects the rising edge of H_NMI. A non-maskable interrupt
is reset by setting the corresponding NMI source enable/
disable bit in the NMI Status and Control Register.
O
CMOS
H_NMI
System Management Interrupt: The H_SMI# is an
output synchronous to LPC clock that is asserted by the
Intel® SCH in response to one of many enabled hardware
or software events.
O
CMOS
H_SMI#
H_STPCLK#
Stop Clock Request: H_STPCLK# is an active-low output
synchronous to LPC clock that is asserted by Intel® SCH in
response to one of many hardware or software events.
When the processor samples H_STPCLK# asserted, it
responds by stopping its internal clock.
O
CMOS
Datasheet
31
INTEL [ INTEL ]
