Signal Description
Power
Well
Signal
Type
Description
Host Address Bus: H_A[31:3]# connect to the processor
address bus. During processor cycles, H_A[31:3]# are
inputs. Note that the address bus is inverted on the
processor bus.
I/O
CMOS
H_A[31:3]#
Core
Host Address Strobe: The source synchronous strobes
are used to transfer H_A[31:3]# and H_REQ[4:0]# at the
2x transfer rate.
I/O
AGTL+
H_ADSTB[1:0]#
H_D[63:0]#
Core
Core
H_ADSTB0# maps to H_A[16:3]#, H_REQ[4:0]#
H_ADSTB1# maps to H_A[31:17]#
Host Data: These signals are connected to the processor
data bus. Note that the data signals are inverted on the
processor bus.
I/O
CMOS
Host Data Strobes: The source synchronous strobes used
to transfer H_D[63:0]# and H_DINV[3:0]# at the 4x
transfer rate.
H_DSTBP[3:0]#
H_DSTBN[3:0]#
I/O
AGTL+
Strobe
Data Bits
Core
Core
H_DSTB[P/N]3#
H_DSTB[P/N]2#
H_DSTB[P/N]1#
H_DSTB[P/N]0#
H_D[63:48]#, H_DINV3#
H_D[47:32]#, H_DINV2#
H_D[31:16]#, H_DINV1#
H_D[15:0]#, H_DINV0#
Hit: This signal indicates that a caching agent holds an
unmodified version of the requested line. Also, driven in
conjunction with H_HITM# by the target to extend the
snoop window.
I/O
CMOS
H_HIT#
Hit Modified: This signal indicates that a caching agent
holds a modified version of the requested line and that this
agent assumes responsibility for providing the line. This
signal is also driven in conjunction with H_HIT# to extend
the snoop window.
I/O
CMOS
H_HITM#
H_LOCK#
Core
Core
Host Lock: All processor bus cycles sampled with the
assertion of H_LOCK# and H_ADS#, until the negation of
H_LOCK# must be atomic.
I
CMOS
Host Request Command: These signals are asserted
during both clocks of the request phase. In the first clock,
the signals define the transaction type to a level of detail
that is sufficient to begin a snoop request. In the second
clock, the signals carry additional information to define the
complete transaction type. The transactions supported by
the Intel® SCH are defined in the Host Interface functional
description section of this document.
I/O
CMOS
H_REQ[4:0]#
H_TRDY#
Core
Core
Host Target Ready: This signal indicates that the target of
the processor transaction is able to enter the data transfer
phase.
O
AGTL+
30
Datasheet
INTEL [ INTEL ]
