Signal Description
2.1
Host Interface Signals
Power
Well
Signal
Type
Description
I/O
AGTL+
Address Strobe: The host bus owner asserts H_ADS# to
indicate the first of two cycles of a request phase.
H_ADS#
Core
Block Next Request: This signal is used to block the
current request bus owner from issuing a new request. This
signal is used to dynamically control the processor bus
pipeline depth.
I/O
CMOS
H_BNR#
H_BPRI#
Core
Priority Agent Bus Request: The Intel® SCH is the only
Priority Agent on the processor bus. It asserts this signal to
obtain the ownership of the address bus. This signal has
priority over symmetric bus requests and will cause the
current symmetric owner to stop issuing new transactions
unless the H_LOCK# signal was asserted.
O
Core
AGTL+
Bus Request 0#: The Intel® SCH pulls the processor bus
H_BREQ0# signal low during H_CPURST#. The signal is
sampled by the processor on the active-to-inactive
transition of H_CPURST#.
I/O
CMOS
H_BREQ0#
Core
Core
H_BREQ0# should be tri-stated after the hold time
requirement has been satisfied.
CPU Reset: H_CPURST# allows the processor to begin
execution in a known state. The Intel® SCH asserts
H_CPURST# and deasserts H_CPUPWRGD upon exit from
its reset. H_CPURST# is deasserted 2–10 ms after
H_CPUPWRGD is asserted.
O
H_CPURST#
AGTL+
Data Bus Busy: This signal is used by the data bus owner
to hold the data bus for transfers requiring more than one
cycle.
I/O
AGTL+
H_DBSY#
Core
Core
Defer: The Intel® SCH will generate a deferred response
as defined by the rules of the dynamic defer policy. The
Intel® SCH will also use the H_DEFER# signal to indicate a
processor retry response.
I/O
AGTL+
H_DEFER#
Dynamic Bus Inversion: These signals are driven along
with the H_D[63:0]# signals. They indicate if the
associated data bus signals are inverted or not.
H_DINV[3:0]# are asserted such that the number of data
bits driven electrically low (low voltage) within the
corresponding 16-bit group never exceeds 8.
I/O
CMOS
H_DINV[3:0]#
Core
H_DINV[x]#
H_DINV3#
H_DINV2#
H_DINV1#
H_DINV0#
Data Bits
H_D[63:48]
H_D[47:32]
H_D[31:16]
H_D[15:0]
Data Power: Used by Intel® SCH to indicate that a data
return cycle is pending within 2 host clock cycles or more.
The processor uses this signal during a read-cycle to
activate the data input buffers in preparation for H_DRDY#
and the related data.
O
H_DPWR#
H_DRDY#
Core
Core
AGTL+
I/O
AGTL+
Data Ready: This signal is asserted for each cycle that
data is transferred.
Datasheet
29
INTEL [ INTEL ]
