Signal Description
2 Signal Description
This chapter provides a detailed description of the Intel® SCH signals and boot strap
definitions. The signals are arranged in functional groups according to their associated
interface (see Figure 2).
Each signal description table has the following headings:
• Signal: The name of the signal/pin
• Type: the buffer direction and type. Buffer direction can be either input, output, or
I/O (bidirectional). See Table 2 for definitions of the different buffer types.
• Power Well: the power plane used to supply power to that signal. Choices are
Core, DDR, Suspend, and RTC.
• Description: A brief explanation of the signal’s function
Table 2.
Intel® SCH Buffer Types
Buffer Type
Buffer Description
Assisted Gunning Transceiver Logic Plus. CMOS Open Drain interface signals
that require termination. Refer to the AGTL+ I/O Specification for complete
details.
AGTL+
CMOS,
CMOS_OD
1.05-V CMOS buffer, or CMOS Open Drain
CMOS buffers for Intel® HD Audio interface that can be configured for either
1.5-V or 3.3-V operation.
CMOS_HDA
CMOS1.8
1.8-V CMOS buffer. These buffers can be configured as Stub Series Termination
Logic (SSTL1.8)
CMOS3.3,
CMOS3.3_OD
3.3-V CMOS buffer, or CMOS 3.3-V open drain
CMOS3.3-5
USB
3.3-V CMOS buffer, 5-V tolerant
Compliant with USB 1.1 and USB 2.0 specifications.
PCI Express interface signals. These signals are compatible with PCI Express
1.0a Signaling Environment AC Specifications and are AC coupled. The buffers
are not 3.3-V tolerant.
PCIE
Serial-DVO differential buffers. These signals are AC coupled. These buffers are
not 3.3-V tolerant.
SDVO
LVDS
A
Low Voltage Differential Signal output buffers. These pure outputs should drive
across a 100-Ω resistor at the receiver when driving.
Analog reference or output maybe used as a threshold voltage or for buffer
compensation.
Datasheet
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INTEL [ INTEL ]
