PCI Express* (D28:F0, F1)
11.2.35 RCAP—Root Capabilities Register
Address Offset:
Default Value:
5eh
0000h
Attribute:
Size:
RO
16 bits
Default
and
Bit
Description
Access
0000h
RO
15:1
0
Reserved
0
RO
Software Visibility of Configuration Retry (SVCR): Maintained for
compatibility
11.2.36 SV_CAPID—Subsystem Vendor Capability ID Register
Address Offset:
Default Value:
90h
0Dh
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
0Dh
RO
Capability Identifier (CID): Value of 0Dh indicates this is a PCI bridge
subsystem vendor capability.
7:0
11.2.37 NXT_PTR3—Next Item Pointer #3 Register
Address Offset:
Default Value:
91h
A0h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
A0h
RO
Next Capability (NEXT): This field indicates the location of the next
capability.
7:0
11.2.38 SVID—Subsystem Vendor Identification Register
Address Offset:
Default Value:
94h–97h
0000h
Attribute:
Size:
R/WO
32 bits
Default
Bit
and
Description
Access
Subsystem Identifier (SID): This field indicates the subsystem as
identified by the vendor. This field is write once and is locked down until a
bridge reset occurs.
00h
R/WO
31:16
15:0
Subsystem Vendor Identifier (SVID): This field indicates the
manufacturer of the subsystem. This field is write once and is locked down
until a bridge reset occurs.
00h
R/WO
198
Datasheet
INTEL [ INTEL ]
