PCI Express* (D28:F0, F1)
11.2.39 PCI—Power Management Capability ID Register
Address Offset:
Default Value:
A0h
01h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
01h
RO
Capability Identifier (CID): Value of 01h indicates this is a PCI power
management capability.
7:0
11.2.40 NXT_PTR4—Next Item Pointer #4 Register
Address Offset:
Default Value:
A1h
00h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
00h
RO
Next Capability (NEXT): This field indicates this is the last capability in
the list.
7:0
11.2.41 PM_CAP—Power Management Capabilities Register
Address Offset:
Default Value:
A2h–A3h
C802h
Attribute:
Size:
RO
16 bits
Default
Bit
and
Description
Access
PME_Support (PMES): This field indicates PME# is supported for states
D0, D3HOT and D3COLD. The root port does not generate PME#, but
reporting that it does is necessary for some legacy operating systems to
enable PME# in devices connected behind this root port.
11001b
RO
15:11
0
RO
10
9
D2_Support (D2S): The D2 state is not supported.
D1_Support (D1S): The D1 state is not supported.
0
RO
000b
RO
Aux_Current (AC): Reports 375 mA maximum suspend well current
required when in the D3COLD state.
8:6
5
0
RO
Device Specific Initialization (DSI): This bit indicates that no device-
specific initialization is required.
0
RO
4
Reserved
0
RO
PME Clock (PMEC): This bit indicates that PCI clock is not required to
generate PME#.
3
010b
RO
Version (VS): This field indicates support for Revision 1.1 of the PCI
Power Management Specification.
2:0
Datasheet
199
INTEL [ INTEL ]
