PCI Express* (D28:F0, F1)
11.2.31 SLSTS—Slot Status Register
Address Offset:
Default Value:
5Ah–5Bh
0000h
Attribute:
Size:
R/WC, RO
16 bits
Default
Bit
and
Description
Access
15:9
00h
Reserved
Link Active State Changed (LASC): This bit is set when the value
reported in Data Link Layer Link Active field of the Link Status register
(D28:F0/F1:52h:bit 13) is changed. In response to a Data Link Layer
State Changed event, software must read Data Link Layer Link Active field
of the Link Status register to determine if the link is active before initiating
configuration cycles to the hot plugged device.
0
8
R/WC
0
RO
7
6
Reserved
Presence Detect State (PDS): If XCAP.SI (D28:F0/F1:42h:bit 8) is set
(indicating that this root port spawns a slot), then this bit:
See
description
0 = Indicates the slot is empty.
1 = Indicates the slot has a device connected.
RO
Otherwise, if XCAP.SI is cleared, this bit is always set (1).
0
RO
MRL Sensor State (MS): Reserved as the MRL sensor is not
implemented.
5
4
0
RO
Command Completed (CC): Hardcoded to 0. These messages are not
supported.
Presence Detect Changed (PDC)
0
3
0 = No change in the PDS bit.
1 = The PDS bit changed states.
R/WC
0
RO
MRL Sensor Changed (MSC): Reserved as the MRL sensor is not
implemented.
2
1
0
0
RO
Power Fault Detected (PFD): Reserved as a power controller is not
implemented.
0
RO
Attention Button Pressed (ABP): Hardcoded to 0. Attention button
messages are not supported.
Datasheet
195
INTEL [ INTEL ]
