PCI Express* (D28:F0, F1)
11.2.44 SMSCS—SMI/SCI Status Register
Address Offset:
Default Value:
DCh–DFh
00000000h
Attribute:
Size:
R/WC, RO
32 bits
Default
Bit
and
Description
Access
Power Management SCI Status (PMCS): This bit is set if the PME
control logic needs to generate an interrupt, and this interrupt has been
routed to generate an SCI.
0
31
R/WC
Hot Plug SCI Status (HPCS): This bit is set if the Hot-Plug controller
needs to generate an interrupt, and has this interrupt been routed to
generate an SCI.
0
30
R/WC
000000h
R/WC
29:5
Reserved
Hot Plug Link Active State Changed SMI Status (HPLAS): This bit is
set when SLSTS.LASC (D28:F0/F1:5A, bit 8) transitions from 0 to 1, and
MPC.HPME (D28:F0/F1:D8h, bit 1) is set. When this bit is set, an SMI# will
be generated.
0
4
3:2
1
R/WC
00b
RO
Reserved
Hot Plug Presence Detect SMI Status (HPPDM): This bit is set when
SLSTS.PDC (D28:F0/F1:5A, bit 3) transitions from 0 to 1, and MPC.HPME
(D28:F0/F1:D8h, bit 1) is set. When this bit is set, an SMI# will be
generated.
0
R/WC
Power Management SMI Status (PMMS): This bit is set when RSTS.PS
(D28:F0/F1:60h, bit 16) transitions from 0 to 1, and MPC.PMME (D28:F0/
F1:D8, bit 1) is set.
0
0
R/WC
11.2.45 FD—Function Disable Register
Address Offset:
Default Value:
FCh–FFh
00000000h
Attribute:
Size:
R/W, R0
32 bits
Default
Bit
31:3
2
and
Access
Description
0
RO
Reserved
Clock Gating Disable (CGD)
0
R/W
0 = Clock gating within this function is enabled.
1 = Clock gating within this function is disabled.
0
RO
1
Reserved
Disable (D)
0
R/W
0
0 = This function is enabled.
1 = This function is disabled.
§ §
202
Datasheet
INTEL [ INTEL ]
