PCI Express* (D28:F0, F1)
11.2.43 MPC—Miscellaneous Port Configuration Register
Address Offset:
Default Value:
D8h–DBh
00110000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
Power Management SCI Enable (PMCE)
0
R/W
0 = SCI generation based on a power management event is disabled.
1 = Enables the root port to generate SCI whenever a power management
event is detected.
31
Hot Plug SCI Enable (HPCE)
0
R/W
0 = SCI generation based on a hot-plug event is disabled.
1 = Enables the root port to generate SCI whenever a hot-plug event is
detected.
30
0
R/W
Link Hold Off (LHO): When set, the port will not take any TLP. This is used
during loopback mode to fill up the downstream queue.
29
0
R/W
Address Translator Enable (ATE): Used to enable address translation by
the AT bits in this register during loopback mode.
28
0h
RO
27:21
20:18
Reserved
100b
R/W
Unique Clock Exit Latency (UCEL): L0s Exit Latency when LCAP.CCC is
cleared.
010b
R/W
17:15
14:12
11:8
7:2
Common Clock Exit Latency (CCEL): L0s Exit Latency LCAP.CCC is set.
000b
R/W
Reserved
0
R/W
Address Translator (AT): During loopback, these bits are XOR'd with bits
[31:28] of the receive address, if the ATE bit in this register is enabled.
0
Reserved
RO
Hot Plug SMI Enable (HPME)
0
R/W
0 = SMI generation based on a Hot-Plug event is disabled.
1 = Enables the root port to generate SMI whenever a Hot-Plug event is
detected.
1
0
Power Management SMI Enable (PMME)
0
R/W
0 = SMI generation based on a power management event is disabled.
1 = Enables the root port to generate SMI whenever a power management
event is detected.
Datasheet
201
INTEL [ INTEL ]
