PCI Express* (D28:F0, F1)
11.2.32 RCTL—Root Control Register
Address Offset:
Default Value:
5Ch–5Dh
0000h
Attribute:
Size:
RO, R/W
16 bits
Default
Bit
and
Description
Access
000h
RO
15:4
Reserved
Power Management Event Interrupt Enable (PIE)
0 = Interrupt generation disabled.
0
R/W
3
1 = Interrupt generation enabled when PCISTS.IS is in a set state (either
due to a 0 to 1 transition, or due to this bit being set with RSTS.IS
already set).
System Error on Fatal Error Enable (SFE)
0
R/W
2
1
0
0 = An SERR# will not be generated.
System Error on Non-Fatal Error Enable (SNE)
0
R/W
0 = An SERR# will not be generated.
System Error on Correctable Error Enable (SCE)
0
R/W
0 = An SERR# will not be generated.
196
Datasheet
INTEL [ INTEL ]
