PCI Express* (D28:F0, F1)
11.2.30 SLCTL—Slot Control Register
Address Offset:
Default Value:
58h–59h
0000h
Attribute:
Size:
R/W, RO
16 bits
Default
and
Bit
Description
Access
000b
RO
15:13
12
Reserved
Link Active Changed Enable (LACE): When set, this field enables
generation of a hot plug interrupt when the Data Link Layer Link Active
field (D28:F0/F1:52h:bit 13) is changed.
0
R/W
0
RO
11
10
Reserved
0
RO
Power Controller Control (PCC): This bit has no meaning for module
based hot-plug.
Power Indicator Control (PIC): When read, the current state of the
power indicator is returned. When written, the appropriate
POWER_INDICATOR_* messages are sent. Defined encodings are:
00b
R/W
Bits
Definition
9:8
00b
01b
10b
11b
Reserved
On
Blink
Off
Attention Indicator Control (AIC): When read, the current state of the
attention indicator is returned. When written, the appropriate
ATTENTION_INDICATOR_* messages are sent. Defined encodings are the
same as the PIC bits above.
00b
R/W
7:6
5
Hot Plug Interrupt Enable (HPE)
0
R/W
0 = Hot plug interrupts based on hot-plug events is disabled.
1 = Enables generation of a hot-plug interrupt on enabled hot-plug events.
Command Completed Interrupt Enable (CCE)
0
R/W
0 = Hot plug interrupts based on command completions is disabled.
1 = Enables the generation of a hot-plug interrupt when a command is
completed by the hot-plug controller.
4
Presence Detect Changed Enable (PDE)
0 = Hot plug interrupts based on presence detect logic changes is
disabled.
1 = Enables the generation of a hot-plug interrupt or wake message when
the presence detect logic changes state.
0
R/W
3
MRL Sensor Changed Enable (MSE)
0 = Indicates that an MRL sensor is not supported.
Power Fault Detected Enable (PFE)
0 = PFE not supported.
0
R/W
2
1
0
R/W
Attention Button Pressed Enable (ABE): ABE is not supported, but is
read/write for ease of implementation and to easily draft off of the PCI-
Express specification.
0
R/W
0
194
Datasheet
INTEL [ INTEL ]
