PCI Express* (D28:F0, F1)
11.2.42 PM_CNTL_STS—Power Management Control and Status
Register
Address Offset:
Default Value:
A4h–A7h
00000000h
Attribute:
Size:
R/W, RO
32 bits
Default
Bit
and
Description
Access
00h
RO
31:16
15
Reserved
0
RO
PME Status (PMES): This bit indicates a PME was received on the
downstream link.
00h
RO
14:9
Reserved
PME Enable (PMEE): This bit indicates PME is enabled. The root port
takes no action on this bit, but it must be R/W for some legacy operating
systems to enable PME# on devices connected to this root port.
0
R/W
8
This bit is sticky and resides in the resume well. The reset for this bit is
RSMRST# which is not asserted during a warm reset.
00h
RO
7:2
Reserved
Power State (PS): This field is used both to determine the current power
state of the root port and to set a new power state. The values are:
00 = D0 state
11 = D3HOT state
00b
R/W
1:0
NOTE: When in the D3HOT state, the controller’s configuration space is
available, but the I/O and memory spaces are not. Type 1
configuration cycles are also not accepted. Interrupts are not
required to be blocked as software will disable interrupts prior to
placing the port into D3HOT. If software attempts to write a 10 or 01
to these bits, the write will be ignored.
200
Datasheet
INTEL [ INTEL ]
