PCI Express* (D28:F0, F1)
11.2.19 BCTRL—Bridge Control Register
Address Offset:
Default Value:
3Eh–3Fh
0000h
Attribute:
Size:
RO, R/W
16 bits
Default
Bit
and
Description
Access
0h
RO
15:12
Reserved
0
RO
Discard Timer SERR# Enable (DTSE): Reserved per PCI Express Base
Specification, Revision 1.0a
11
10
9
0
RO
Discard Timer Status (DTS): Reserved per PCI Express Base
Specification, Revision 1.0a.
0
RO
Secondary Discard Timer (SDT). Reserved per PCI Express Base
Specification, Revision 1.0a.
0
RO
Primary Discard Timer (PDT): Reserved per PCI Express Base
Specification, Revision 1.0a.
8
0
RO
Fast Back to Back Enable (FBE): Reserved per PCI Express Base
Specification, Revision 1.0a.
7
0
R/W
Secondary Bus Reset (SBR): Triggers a hot reset on the PCI Express
port.
6
0
RO
5
Master Abort Mode (MAM): Reserved per Express specification.
VGA 16-Bit Decode (V16)
0
R/W
0 = VGA range is enabled.
1 = The I/O aliases of the VGA range (see BCTRL:VE definition in Bit 3)
are not enabled, and only the base I/O ranges can be decoded.
4
3
VGA Enable (VE)
0 = The ranges below will not be claimed off the backbone by the root
port.
1 = The following ranges will be claimed off the backbone by the root port:
0
R/W
• Memory ranges A0000h–BFFFFh
• I/O ranges 3B0h – 3BBh and 3C0h – 3DFh, and all aliases of bits
15:10 in any combination of 1s
ISA Enable (IE): This bit only applies to I/O addresses that are enabled
by the I/O Base and I/O Limit registers and are in the first 64 KB of PCI
I/O space.
0
R/W
0 = The root port will not block any forwarding from the backbone as
described below.
2
1 = The root port will block any forwarding from the backbone to the
device of I/O transactions addressing the last 768 bytes in each 1 KB
block (offsets 100h to 3FFh).
SERR# Enable (SE)
0
R/W
0 = The messages described below are not forwarded to the backbone.
1 = ERR_COR, ERR_NONFATAL, and ERR_FATAL messages received are
forwarded to the backbone.
1
0
Parity Error Response Enable (PERE)
0 = Poisoned write TLPs and completions indicating poisoned TLPs will not
set the SSTS.DPD (D28:F0/F1:1Eh, bit 8).
1 = Poisoned write TLPs and completions indicating poisoned TLPs will set
the SSTS.DPD (D28:F0/F1:1Eh, bit 8).
0
R/W
Datasheet
185
INTEL [ INTEL ]
