PCI Express* (D28:F0, F1)
11.2.9
HEADTYP—Header Type Register
Address Offset:
Default Value:
0Eh
81h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
Multi-Function Device (MFD)
1
RO
7
0 = Single-function device.
1 = Multi-function device.
Configuration Layout (CL): Indicates the header layout of the
configuration space, which is a PCI-to-PCI bridge, indicated by 1h in this
field.
01h
RO
6:0
11.2.10 BNUM—Bus Number Register
Address Offset:
Default Value:
18–1Ah
000000h
Attribute:
Size:
R/W
24 bits
Default
Bit
and
Description
Access
00h
R/W
Subordinate Bus Number (SBBN): Indicates the highest PCI bus
number below the bridge.
23:16
15:8
7:0
00h
R/W
Secondary Bus Number (SCBN): Indicates the bus number the port.
00h
R/W
Primary Bus Number (PBN): Indicates the bus number of the
backbone.
11.2.11 SLT—Secondary Latency Timer
Address Offset:
Default Value:
1Bh
00h
Attribute:
Size:
RO
8 bits
Default
Bit
and
Description
Access
00h
RO
Secondary Latency Timer (SLT): Reserved for a Root Port per the PCI
Express Base Specification.
7:0
Datasheet
181
INTEL [ INTEL ]
