PCI Express* (D28:F0, F1)
11.2.25 DSTS—Device Status Register
Address Offset:
Default Value:
4Ah–4Bh
0010h
Attribute:
Size:
R/WC, RO
16 bits
Default
Bit
and
Description
Access
00h
RO
15:6
5
Reserved
Transactions Pending (TDP): This bit has no meaning for the root port
since only one transaction may be pending to the Intel® SCH, so a read of
this bit cannot occur until it has already returned to 0.
0
RO
1
RO
AUX Power Detected (APD): The root port contains AUX power for wake
up.
4
3
0
Unsupported Request Detected (URD): This bit indicates an
unsupported request was detected.
R/WC
Fatal Error Detected (FED): This bit indicates a fatal error was
detected.
0
2
1
0 = No fatal errors have occurred.
1 = A fatal error occurred from a data link protocol error, link training
error, buffer overflow, or malformed TLP.
R/WC
Non-Fatal Error Detected (NFED): This bit indicates a non-fatal error
was detected.
0
0 = Non-fatal has not occurred.
R/WC
1 = A non-fatal error occurred from a poisoned TLP, unexpected
completions, unsupported requests, completer abort, or completer
timeout.
Correctable Error Detected (CED): This bit indicates a correctable error
was detected.
0
0 = Correctable has not occurred.
0
R/WC
1 = The port received an internal correctable error from receiver errors/
framing errors, TLP CRC error, DLLP CRC error, replay num rollover,
replay timeout.
Datasheet
189
INTEL [ INTEL ]
